We present a fabricated and experimentally characterized memory stack that unifies memristive and memcapacitive behavior. Exploiting this dual functionality, we design a circuit enabling simultaneous control of spatial and temporal dynamics in recurrent spiking neural networks (RSNNs). Hardware-aware simulations highlight its promise for efficient neuromorphic processing.

Phase change memories (PCMs) are at the heart of modern memory technology, offering multi-level storage, fast read/write operations, and non-volatility, bridging the gap between volatile DRAM and non-volatile Flash. The reversible transition between amorphous and crystalline states of phase-change materials such as GeTe or Ge2Sb2Te5 is at the basis of PCM devices. Despite their importance, PCM devices face challenges including high power consumption during the RESET operation. Current research efforts focus on improving device architecture and exploring alternative phase-change materials such as GeTe/Sb2Te3 super-lattices (SLs), for which a reduced programming power consumption is observed compared with standard PCMs. Herein, by combining X-ray diffraction and scanning transmission electron microscopy imaging of SL thin films with the study of the same SL in PCM devices, it is shown that it is possible to significantly decrease RESET energy of the device, without modifying the SL composition, by reducing the amount of structural defects through annealing treatment. The best device properties are obtained after transforming the SL into a defect-free, highly out-of-plane oriented rhombohedral phase. These results offer a promising avenue for further improving the performance of SL-based PCM devices through structural optimization.

Resistive Random Access Memory (RRAM) technologies represent a promising frontier in next-generation non-volatile memory devices. They combine an operating speed and endurance superior to Flash memories with cost-effectiveness that challenges DRAMs. This paper delves into the RRAM challenges, examining the fault distribution in advanced RRAM configurations and the interplay between existing error correction codes (ECCs) and design assist techniques like Write Verify Algorithms. Our investigation reveals the limitations of current approaches and underscores the necessity for a holistic system-level fault detection, analysis, and repair solution. Through a comprehensive case study, we introduce and evaluate a novel scheme aimed at co-optimizing these elements to enhance RRAM reliability. The contributions of this work not only address a critical gap in the current understanding and application of RRAM but also lay the groundwork for future research and development in memory technologies.

This study explores the reliability of a phase-change memory (PCM) cointegrated with an ovonic threshold switching (OTS) selector (one selector and one memory [1S1R] structure) based on an innovative double-patterned self-aligned architecture. The variability of the threshold voltage (Vth$\left(\text{V}\right)_{\text{th}}$) for both the SET and RESET states is examined, comparing different distribution models to validate the use of mean and standard deviation as viable metrics. The dispersion of Vth$\left(\text{V}\right)_{\text{th}}$ is tracked under different programming conditions to provide insight into the evolution of device behavior over SET/RESET, endurance cycles, and read cycles. The PCM device is based on a "wall" structure and on Ge2Sb2Te5 alloy, while the OTS is based on a GeSbSeN alloy. The analysis focuses on the programming characteristics and SET pulse optimization, studying current control and pulse fall times. The results are based on statistical data obtained from a kb-sized memory array. A memory window of over 2 V is achieved. The research helps understanding the DPSA architecture, and PCM + OTS in general, offering insights into their programming, variability, and reliability targeting crossbar applications. The article addresses the interplay of phase-change memory and ovonic threshold switching selectors in a novel double-patterned self-aligned architecture. A statistical analysis of programming, SET speed, reading, and cycling endurance is conducted. The viability of this technology is assessed on a kb-sized array by comparing different distribution models, resulting in the achievement of a memory window exceeding 2 V.image (c) 2024 WILEY-VCH GmbH

This work presents a novel mechanism for 1R a-V2O3 ReRAM cells fabricated with "wall" integration. Non-volatile Resistive Switching (RS) implies a Vanadium (V) depleted zone created during a unique initialisation step - highlighted by simulation, electrical and physicochemical characterisations. This new a-V2O3 based ReRAM features large memory window, high RS speed, excellent scalability and good endurance.

An increasing number of neuroscience studies are highlighting the importance of spatial dendritic branching in pyramidal neurons in the brain for supporting non-linear computation through localized synaptic integration. In particular, dendritic branches play a key role in temporal signal processing and feature detection, using coincidence detection (CD) mechanisms, made possible by the presence of synaptic delays that align temporally disparate inputs for effective integration. Computational studies on spiking neural networks further highlight the significance of delays for CD operations, enabling spatio-temporal pattern recognition within feed-forward neural networks without the need for recurrent architectures. In this work, we present DenRAM, the first realization of a spiking neural network with analog dendritic circuits, integrated into a 130nm technology node coupled with resistive memory (RRAM) technology. DenRAM's dendritic circuits use the RRAM devices to implement both delays and synaptic weights in the network. By configuring the RRAM devices to reproduce bio-realistic timescales, and through exploiting their heterogeneity, we experimentally demonstrate DenRAM's capability to replicate synaptic delay profiles, and efficiently implement CD for spatio-temporal pattern recognition. To validate the architecture, we conduct comprehensive system-level simulations on two representative temporal benchmarks, highlighting DenRAM's resilience to analog hardware noise, and its superior accuracy compared to recurrent architectures with an equivalent number of parameters. DenRAM not only brings rich temporal processing capabilities to neuromorphic architectures, but also reduces the memory footprint of edge devices, provides high accuracy on temporal benchmarks, and represents a significant step-forward in low-power real-time signal processing technologies.

Resistive Random Access Memories (ReRAM) arrays provides a promising basement to deploy neural network accelerators based on near or in memory computing. However most popular accelerators rely on Ohm’s and Kirchhoff’s laws to achieve multiply and accumulate, and thus are prone to ReRAM variability and voltage drop in the memory array, and thus need sophisticated readout circuits. Here we propose a robust binary neural network, based on fully differential capacitive neurons and ReRAM synapses, used in a resistive bridge fashion. We fabricated a network layer with up to 23 inputs that we extrapolated to large numbers of inputs through simulation. Defining proper programming and reading conditions, we demonstrate the high resilience of this solution with a minimal accuracy drop, compared to a software baseline, on image classification tasks. Moreover, our solution can achieve a peak energy efficiency, comparable with the state of the art, when projected to a 22 nanometer technology.

This paper presents an outlook of Crossbar memory array capabilities while operated in the sub-threshold regime. By means of experimental data obtained on a RRAM resistive device co-integrated in series with an OTS back-end selector, the pertinence of 1S1R sub-threshold read operation for both standard Binarized Neural Networks (BNNs) and Binarized Spiking Neural Networks (B'SNNs) inference implementation in hardware is elucidated.

Safety-critical sensory applications, like medical diagnosis, demand accurate decisions from limited, noisy data. Bayesian neural networks excel at such tasks, offering predictive uncertainty assessment. However, because of their probabilistic nature, they are computationally intensive. An innovative solution utilizes memristors' inherent probabilistic nature to implement Bayesian neural networks. However, when using memristors, statistical effects follow the laws of device physics, whereas in Bayesian neural networks, those effects can take arbitrary shapes. This work overcome this difficulty by adopting a variational inference training augmented by a "technological loss", incorporating memristor physics. This technique enabled programming a Bayesian neural network on 75 crossbar arrays of 1,024 memristors, incorporating CMOS periphery for in-memory computing. The experimental neural network classified heartbeats with high accuracy, and estimated the certainty of its predictions. The results reveal orders-of-magnitude improvement in inference energy efficiency compared to a microcontroller or an embedded graphics processing unit performing the same task.

Deep learning has made remarkable progress in various tasks, surpassing human performance in some cases. However, one drawback of neural networks is catastrophic forgetting, where a network trained on one task forgets the solution when learning a new one. To address this issue, recent works have proposed solutions based on Binarized Neural Networks (BNNs) incorporating metaplasticity. In this work, we extend this solution to quantized neural networks (QNNs) and present a memristor-based hardware solution for implementing metaplasticity during both inference and training. We propose a hardware architecture that integrates quantized weights in memristor devices programmed in an analog multi-level fashion with a digital processing unit for high-precision metaplastic storage. We validated our approach using a combined software framework and memristor based crossbar array for in-memory computing fabricated in 130 nm CMOS technology. Our experimental results show that a two-layer perceptron achieves 97% and 86% accuracy on consecutive training of MNIST and Fashion-MNIST, equal to software baseline. This result demonstrates immunity to catastrophic forgetting and the resilience to analog device imperfections of the proposed solution. Moreover, our architecture is compatible with the memristor limited endurance and has a 15× reduction in memory footprint compared to the binarized neural network case.

Single memristor crossbar arrays are a very promising approach to reduce the power consumption of deep learning accelerators. In parallel, the emerging bio-inspired spiking neural networks (SNNs) offer very low power consumption with satisfactory performance on complex artificial intelligence tasks. In such neural networks, synaptic weights can be stored in nonvolatile memories. The latter are massively read during inference, which can lead to device failure. In this context, a 1S1R (1 Selector 1 Resistor) device composed of a HfO2-based OxRAM memory stacked on a Ge-Se-Sb-N-based ovonic threshold switch (OTS) back-end selector is proposed for high-density binarized SNNs (BSNNs) synaptic weight hardware implementation. An extensive experimental statistical study combined with a novel Monte Carlo model allows to deeply analyze the OTS switching dynamics based on field-driven stochastic nucleation of conductive dots in the layer. This allows quantifying the occurrence frequency of OTS erratic switching as a function of the applied voltages and 1S1R reading frequency. The associated 1S1R reading error rate is calculated. Focusing on the standard machine learning MNIST image recognition task, BSNN figures of merit (footprint, electrical consumption during inference, frequency of inference, accuracy, and tolerance to errors) are optimized by engineering the network topology, training procedure, and activations sparsity.

In this article, we investigate the influence of germanium content in GeSbSeN-based ovonic threshold switching (OTS) selector devices. We performed physico-chemical analyses on five different Gex(SbSe)1–xN alloys to understand how the germanium content influences the material structure and its integrity once submitted to temperatures up to 400 °C. Thanks to the electrical characterization of Gex(SbSe)1–xN OTS devices, we analyze the evolution of the electrical parameters along cycling up to 108 cycles and before and after annealing at 400 °C. Cycle -to -cycle variability and drift phenomenon are also investigated. Finally, we demonstrate how Ge content should be properly tuned to improve the thermal stability of the alloy without affecting the leakage current and the electrical parameters’ variability.

Sb-rich GeSbTe-based phase-change memories (PCMs) were studied in the past years for their high switching speed to target storage class memory (SCM) applications. In this work, we show the advantages of an engineered multilayered Sb-rich GeSbTe stack compared with standard bulk reference materials. The studied multilayer-based PCM devices feature a lower programming current with respect to the equivalent bulk ones, preserving a high programming speed. Furthermore, multilayered Sb-rich GeSbTe brings better endurance performances for a wide programming current range and extremely reduced cycle-to-cycle (C2C) and device-to-device (D2D) variability along cycling verified in 4 kb PCM arrays. These results confirm improved yield and reliability obtained, thanks to multilayered PCM solution.

Crossbars of resistive memories, or memristors, provide a road to reduce the energy consumption of artificial neural networks, by naturally implementing multiply accumulate operations, their most basic calculations. However, a major challenge of implementing robust hardware neural networks is the conductance instability over time of resistive memories, due to the local recombination of oxygen vacancies. This effect causes resistive memory‐based neural networks to rapidly lose accuracy, an issue that is sometimes overlooked. Herein, this conductance instability issue is shown, which can be avoided without changing the material stack of the resistive memory by exploiting an original programming strategy. This technique relies on program‐and‐verify loops with appropriately chosen wait times and ensures that the resistive memories are programmed into states with stable filaments. To test the strategy, a 32 × 32 in‐memory computing system, fabricated in a hybrid complementary metal‐oxide‐semiconductor (CMOS)/hafnium oxide technology, is programmed to classify heart arrhythmia from electrocardiogram. When the resistive memories are programmed conventionally, the system loses accuracy within hours. In contrast, when using this technique, the system maintains an accuracy of 95% over more than 2 months. These results highlight the potential of resistive memory for the implementation of low‐power neural networks with long‐term stability.

2022 International Conference on Solid State Devices and Materials ,Breaking the Thermal Stability Limit of Phase-Change Materials for Embedded Memory thanks to Innovative N-doped GeSe1-xTex Alloys

Innovative nanocomposites consisting of [(GeTe) 4 nm/ C 1 nm ] 10 multilayers (MLs) deposited by magnetron sputtering are integrated in phase‐change memory (PCM) test devices with a “wall structure.” Scanning transmission electron microscopy (STEM) shows that an ML structure, with crystallized GeTe layers, is kept after integration in as‐fabricated devices and also after an additional annealing of the devices at 425 °C. The programming current (RESET current) required to reach the high resistance state of [(GeTe) 4 nm /C 1 nm ] 10 ML devices decreases by 45% after annealing at 425 °C. The reduction in RESET current is 55% and the reduction in drift coefficient is about 40% in ML devices annealed at 425 °C compared to similar devices incorporating Ge 2 Sb 2 Te 5 . STEM imaging, coupled with nano‐beam electron diffraction and electron energy loss spectroscopy, of ML devices in the high resistance state shows that the RESET current reduction after annealing is correlated to a reduction of the amorphized volume.

Real-world sensory-processing applications require compact, low-latency, and low-power computing systems. Enabled by their in-memory event-driven computing abilities, hybrid memristive-Complementary Metal-Oxide Semiconductor neuromorphic architectures provide an ideal hardware substrate for such tasks. To demonstrate the full potential of such systems, we propose and experimentally demonstrate an end-to-end sensory processing solution for a real-world object localization application. Drawing inspiration from the barn owl's neuroanatomy, we developed a bio-inspired, event-driven object localization system that couples state-of-the-art piezoelectric micromachined ultrasound transducer sensors to a neuromorphic resistive memories-based computational map. We present measurement results from the fabricated system comprising resistive memories-based coincidence detectors, delay line circuits, and a full-custom ultrasound sensor. We use these experimental results to calibrate our system-level simulations. These simulations are then used to estimate the angular resolution and energy efficiency of the object localization model. The results reveal the potential of our approach, evaluated in orders of magnitude greater energy efficiency than a microcontroller performing the same task.