Low sensitivity, long recovery times and unstable ability at high humidity has become a problem to develop humidity sensors. To overcome these problems, iron sesquioxide/carbon nanotube (Fe2O3/CNT) composite was prepared by hydrothermal technique as the humidity sensor material. The results of XRD and FI-IR reveal that Fe2O3/CNT with abundant hydrophilic functional groups are successfully synthesized. Meanwhile, First-principles (DFT) results demonstrate that Fe2O3 has higher binding energy and density of states (DOS) peak shift when worked with water molecules than ferric oxide (Fe3O4), indicating it has better adsorption kinetics thus to high humidity sensitivity on the surface. Furthermore, the capability of the Fe2O3 material to sense humidity was investigated via hysteresis and response/recovery test. Based on the hydrophilic functional groups and high adsorption capacity for water molecules, when compared with Fe3O4-based humidity sensor, this Fe2O3/CNT device has an excellent humidity sensitivity, which display low hysteresis, good repeatability, and short response time. This work suggests that Fe2O3/CNT could be a promising candidate material for developing high-performance humidity sensor.

Charge pump is an important module in analog phase - locked loop. The mismatch current greatly affects the in-band noise of CPPLL. To reduce the charge pump mismatch current to improve the overall noise performance of the PLL. In order to reduce the influence of channel length modulation effect on current source, a compensation current is added to the current source of traditional charge pump, and the current is determined by feedback loop. The simulation results show that when the output voltage ranges from 0.4V to 2.8V after the addition of the structure, the charge-discharge mismatch ratio decreases from 7.9% to 0.34%. Thus, the noise performance of the PLL is greatly improved.

研究一种高精度CMOS带隙基准电压源(BGR)电路,BGR电路由两个核心和一个曲率校正电路组成,包括电流镜和求和电路.两个核心电路采用传统电路结构,并具有向下的曲率特性.提出一种利用电流镜像电路来实现具有向上曲率特性的BGR核心.在BGR中选择合适的电阻,可以得到一个参考电压具有良好平衡的曲率下降特性,而另一个参考电压具有均匀平衡向上的曲率特性.将两个参考电压的相加以实现高阶曲率补偿.在3.3V电源电压供电情况下,采用0.13 μm CMOS工艺可以产生1.2V的基准电压,在200℃(-45℃～155℃)的宽温度范围内,使所提出的BGR电路的温度系数低至1.45 ppm/℃.电源抑制比为-67.5 dB@100 Hz、-45.0 dB@100 KHz,消耗电流为911 nA.

Flexible, biocompatible temperature sensors are of great importance for future developments in wearable electronic skin. Herein, a high resolution, fast response, biocompatible negative temperature coefficient (NTC) temperature sensor comprised of poly (3,4-ethylenedioxythiophene): poly (styrenesulfonate) (PEDOT: PSS) and phthalocyanine copper (CuPc) is developed. The addition of CuPc with high electron mobility to PEDOT: PSS increases the effective electron transition under the action of thermal energy, and thus its thermoelectric performance of the material is improved. The packaged sensor can monitor temperature changes in the range of 20 degrees C to 80 degrees C in real time with high sensitivity (0.1940% degrees C-1), linearity (R-2 =0.994) and accuracy (0.1 degrees C). When the ambient temperature of the sensor changes from 25 degrees C to 50 degrees C, the response and recovery time of the sensor are similar to 1 s. The performance of the sensor has not decreased significantly after 4 weeks of continuous operation, which validates the high reliability of the sensor in the extended working time. Furthermore, the comparison between the PEDOT: PSS/CuPc sensor and commercial infrared thermal imager on different parts of the human body temperature measurement shows that the PEDOT: PSS/CuPc sensor is applicable in electronic skin, medical detection and other fields.

基于当前一些高集成度高精度应用领域时钟信号大量需求的目的,介绍了一种具有高阶温度补偿的高精度RC振荡器.文中所设计的电流源电路采用了3阶温度补偿的方法,可以有效降低电路对温度变化的敏感性,利用具有超低温度系数的电流对电容进行充放电,实现在较宽的温度范围内振荡器频率的高稳定性.仿真结果表明:在电源电压范围为2.5 V～5.5 V,温度范围为-40℃～125℃,及不同的工艺角下,输出频率精度保持在±0.25%以内.该RC振荡器具有高精度的输出频率,能够作为一些数模混合电路的时钟信号.

在芯片设计的流程中至关重要的一环就是对于芯片的验证.APB接口作为一种AMBA总线接口协议,被大面积应用于各类SoC芯片中.当使用APB接口进行数据搬移时,需要DMA模块与CPU进行信号交互,由此带来APB接口与DMA模块联合验证的需求,而不同的IP核对于功能覆盖点有不一致的要求.针对不同的IP核,提出一种针对APB接口与DMA联动的验证结构,可通用于各种IP核的APB接口与DMA联动验证,增强了验证模块的可重用性.通过UVM体系的验证,通用功能覆盖率达到100％,符合业内的实际生产需求覆盖率.

基于CSMC.25 μm BCD工艺模型和BG电路结构中的三极管VBE的负温度系数,与恒流源和数据选择器所产生的高低阈值电压的比较,得到一种高精度的过温保护电路.通过Cadence IC51 Spectre软件仿真平台仿真验证,在典型的模型(tt)仿真情况下,当温度大于166.4℃时,输出由低变高,控制信号迫使整个芯片关断;当温度低于132℃时,输出电平由高转为低,电路恢复正常工作状态.设置的电源电压范围在3.7 ～5 V时,过温的阈值变化仅为0.3V,由此可见温度的变化精度高.

A passive microfluidically tunable power divider (PD) with a wide-frequency-agile range based on substrate integrated waveguide (SIW) has been presented. The proposed structure consists of two SIW resonators loaded on the same complementary split-ring resonator and five identical filling-water tubes placed on the top plane. By injecting water into five tubes, the effective permittivity of the substrate can be controlled, and thus the operating frequency of the PD can be precisely tuned. For demonstration, the proposed PD is designed and fabricated. The measured and simulated results are given, showing good agreement.

文章设计了一种基于一款LED驱动芯片BOOST环路的电流采样电路,采用一种电路原理简单且输出损耗小的功率开关管导通电阻的方式,来实现电路采样功能.设计了数字电路模块控制采样电路的启动与关断,保证电路在整个芯片工作时处于正常的工作点.利用BCD工艺,在电源电压为3.7 V下对电路进行仿真验证,仿真后的结果与理论值基本一致,表明该电路能很好地采样电感电流,在LED芯片中正常的工作.

A new 500-V ON-state breakdown voltage (ON-BV) parasitic JFET is proposed in this paper. Compared with traditional structures, a special junction field-effect transistor (JFET) region is located at the edge of the LDMOS. The drift region length of the JFET is larger than that of the LDMOS region. When JFET works in high-voltage on-state, the carriers are separated from the LDMOS region by a transition region close to the JFET region. Then the peak electric field and the impact ionization rate are suppressed. It helps the device to achieve the high ON-BV. Experimental results show that the ON-BV of the proposed structure is larger than 500 V, which is far larger than that of the traditional structures. In addition, the OFF-state breakdown voltage is 550 V.

In this paper, a $0.18~{\mu }\text{m}$ n-type lateral DMOS (LDMOS) is researched. By optimized manufacture process and device structures, ultra-low specific on resistance ( ${R} _{\mathrm {onsp}}$ ) is achieved. Pbody and n-type drift region are all full self-aligned implantation (FSAI). For different structures, the uniformities of the dc parameters affected by the process variation are researched. Experimental results show that: by optimizing manufacture process and device structures, the FSAI nLDMOS has competitive ${R} _{\mathrm {onsp}}$ compared with other technologies. For Breakdown voltage equals to 42 V and 52 V, the ${R} _{\mathrm {onsp}}$ are 18.7 $\text{m}{\Omega \bullet }$ mm 2 and 30 $\text{m} {\Omega \bullet }$ mm 2 , respectively. For FSAI-nLDMOS, both simulation and experiment demonstrated that the shift of the dc parameters generated by the process variation is superior to the other technologies. Moreover, only one n-type drift region with filed oxide is used. The device is fabricated in bulk-silicon without epitaxy. These leads to the low cost of the fabrication.

Banba结构是模拟电路中基准源部分的一个基本结构.在针对高阶补偿Banba结构的带隙基准源设计中,其高阶补偿电阻的实际版图大小占整体面积的50％以上.提出了对于高阶补偿Banba结构的改进论证,主要对高阶补偿电阻的有无进行仿真分析,得到对其结构的改善方法.在经过一定的优化后可为大部分通用电路提供稳定低温漂的供电或激励.

如今集成电路工艺更多采用的是CMOS工艺,因为具有功耗低便于集成等特点.但BJT工艺仍然有不可替代的优点,它具有电驱动能力强上电速度快的特点,且工艺简单,成本更低,在需要高功率大电压的环境中,采用BJT工艺仍然是不错的选择.提出了一种基于BJT工艺的无运放低温度系数的带隙基准源,适用温度范围广,在-40℃～140℃都具有较好的温度特性.该电路采用重庆二十四所的WX40工艺,测试结果显示能产生较高精度的3.3V电压源,且电压源抑制比高达85 dB,同时具有极高的线性调整率,可以在11～40 V的电压范围下工作,温漂系数为14 PPM.

文章基于通过控制mos管的栅极电压产生随着温度变化的补偿电流原理,采用0.5μm BCD30 V工艺,设计一款二阶温度补偿带隙基准电压源,仿真结果表明,电源电压等于7 V时,电路能够产生一个稳定的1.24 V输出电压,在﹣40～125℃内,最小温度系数为3.47×10-6/℃,最大温度系数为6.5×10-6/℃,输出电压偏差3 mV.在7 V电源电压下,100 kHz频率下电源抑制比为65 dB.

The dynamic on-resistance (RON) problem widely exists in reduced surface field (RESURF) lateral DMOS (LDMOS), which leads to large conduction losses in the switching application. Analysing a 700-V triple RESURF LDMOS, the mechanism of this phenomenon is researched by the analytical model and the experimental results. Building some bridges of the p-type buried layer (Pbury), the charges of the Pbury-N-well capacitanceare discharged. The Vds can be reduced to the static value quickly without the tail. Therefore, the dynamic RON is significantly reduced. Meanwhile, the breakdown voltage is not affected by the Pbury bridge.

LIHT (Lack Injection of Hole Termination) structure is proposed and studied. Compared with conventional termination structure, the novel structure features a partial N-doped anode in the transition region and termination region instead of a whole P-doped anode. The LIHT structure stores less carries in the drift region of the transition region and termination region, in which holes concentration reduced by 3 orders of magnitude that from 10 14 cm -3 in conventional structure to 10 11 cm -3 . It will decrease the holes quantity need to be extracted from the transition region when turning the IGBT off and avoid the existence of hole current crowding at the corner of the guard ring. With the LIHT structure, the risen lattice temperature is reduced by 27.5K during turn-off compared with conventional structure. Therefore the LIHT structure eliminates the phenomenon of over-current and over-temperature in the transition region, which makes the device own ultra robust turn-off capability. Based on the concept of current crowding effect, the authors attempt to propose a thermal runaway failure (TRF) model to predict the maximum current can be turned off.

A reference source for generating a low temperature drift coefficient,low temperature coefficient bandgap reference source without operational amplifiers is proposed in this paper.By using higher-order temperature compensation technology,the reference voltage with lower temperature coefficient is achieved.The second-order temperature compensation circuit constructed by MOSFET.Current mirror is used to realize the PTAT current,without the operational amplifier,Then,The chip area is reduced.The 0.5 μm BCD process is used to design the circuit.Working in 5.8 V power supply,when the temperature changes from-40 ℃ to 150 ℃,the reference voltage varies from 1.26 to 1.262 V,the temperature drift coefficient is only 8.07×10-6/℃.

The degradation of ON-resistance (RON) caused by the hot-carrier injection in the 700 V triple reduce SURface field LDMOS is investigated in this letter. Experimental results show that the degradation of RON is reduced by increasing the dose of p-type buried layer (Pbury). The average Ron shift is only 3.7% after 168 h of aging tests with Pbury dose equal to 3.4 × 1012 cm-2. Both peak electric field and impact ionization rate near the bird's beak close to the source are decreased by increasing the dose of Pbury. Meanwhile, the peak electric field close to the drain is increased to avoid the drop in the breakdown voltage.

采用直接数字频率合成激励锁相环方案,基于现场可编程门阵列串行高速控制方式,设计并实现了一种低杂散、低相位噪声的C波段雷达跳频频率源.通过对有源环路滤波器参数和印制电路板的优化设计,使相位噪声和杂散等关键指标得到了极大改善.对系统设计方案、m序列发生器、跳频时间和相位噪声模型做了详细的理论分析和估算.测试结果表明:在7.5 GHz处,相位噪声≤-100 dBc/Hz@100 kHz,杂散电平≤-65 dBc,跳频时间≤10μs,输出功率＞10 dBm,实测结果满足产品的设计指标要求.

采用2种复合工艺流程在900℃和950℃制备了适用于低温共烧陶瓷(LTCC)工艺的Ni-Cu-Zn铁氧体/BaTiO3复合材料.对比研究了不同工艺流程下,烧结温度及助剂用量变化对复合体系烧结性能和电磁性能的影响.900℃烧结时,在铁氧体预烧前添加BaTiO3(工艺流程Ⅱ)制备的复合材料比在铁氧体预烧后添加BaTiO3(工艺流程Ⅰ)制备的复合材料有更高的烧结密度(5.40g/cm3)和Snoek乘积(5.56GHz);950℃烧结时,工艺流程Ⅱ制备的复合材料的介电性能优于工艺流程Ⅰ制备的.