Ultra-Thin-Body and Back-oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) MOSFETs are the most recent and advanced Silicon-On-Insulator (SOI) architecture proposed to overcome the down-scaling limitations of traditional bulk devices. The UTBB-FDSOI architecture has already been proved very attractive for RF-mmW circuits thanks to the excellent reported RF figure of merits (FOMs). In this article, we report on an experimental investigation of the back gate biasing impact on the high-frequency (HF) noise performances of an advanced 22 nm UTBB-FDSOI technology developed by GLOBALFOUNDRIES. For the lower gate voltages, the back gate biasing was shown to decrease by one third the equivalent noise resistance (Rn). Moreover, a 3 dB increase for the associated gain (Ga) was achieved at Vg=0.3V. A relaxed contacted-poly-pitch was also shown to decrease Rn by 11%.

the drastic downscaling of the transistor size along with advances in material sciences allowed the development of low power CMOS technologies with competitive RF figure of merits for millimeter wave applications. In this context, this paper presents the RF characterization (up to 50 GHz) of an advanced 22nm UTBB FDSOI technology developed by Globalfoundries. In addition to the DC performances with a DC transconductance of 1.6 S/mm, this technology presents promising RF characteristics with a Ft/F max above 330 GHz. Also, it is shown that the device's gate finger width can be decreased down to 0.3 μm without RF performance degradation. Furthermore, the relaxed contacted poly pitch is shown to have favorable impact on F max .

The drastic downscaling of the transistor size along with advances in material sciences allowed the development of low power CMOS technologies with competitive RF figure of merits suitable for millimeter applications. In this context, this paper presents the RF and noise characterization (up to 110 GHz) of an advanced 22 nm UTBB FDSOI technology developed by Globalfoundries. In addition to the excellent DC performance, the technology presents promising RF characteristics. Indeed, a maximum transconductance of 1.78 S/mm and a F max of 435 GHz are achieved. The technology also offers a state-of-the-art minimum noise figure (NF min ) of 0.45 dB at 20 GHz (with an associated Gain of 13 dB) for a drain current of 185 mA/mm.

High speed 3D interconnects are a key element in 2.5D interposer technology that is widely investigated for high performance applications. A wide-band electrical modeling and optimization method of the photonic interposer interconnect chains is presented using scalable models developed based on electromagnetic simulations. Resulting models enable fast and accurate assessment of the whole-chain performances for various sets of technology and design parameters. Using these tools, transmission of 100-Gbps signal through Back-end-of-Line (BEOL), Through Silicon Via (TSV) and Redistribution Layer (RDL) chains are improved following two different methods: independent optimization of each interconnect and optimization of the whole chain. Both techniques are compared for TSV-RDL chain case with wide-range parameter variation and for BEOL-TSV-RDL path satisfying design and technology constraints. Optimization results are validated through comparison with 3D-EM simulation, demonstrating the efficiency of proposed methods to optimize the entire 3D-chain. Results would lead to further works including eye-diagram opening and power consumption optimization, geometrical discontinuity modeling and optimized chain integration.

This paper proposes an extensive analysis of the impact of both structural effect and charge parameters on silicon nanowire-based biological sensors, for single-charge detection. These parameters are calibrated on physical and electrical characterizations and are subsequently introduced in a compact model to predict the signal over noise ratio (SNR). We finally propose rules for the design of nanowires and recommendations for the placement of the biological element, inducing the single charge release.

Tandem GaInP/GaAs//Si(inactive) solar cells were manufactured by direct wafer bonding under vacuum. At this early stage, an inactive silicon substrate was used (i.e. n+ Si substrate instead of an active n-p Si junction). Bonded devices presented an S-shaped J-V curve with a kink close to Voc caused by a built-in potential barrier at the III-V//Si interface that reduces the fill factor and therefore the efficiency of the device by 7% compared to the stand-alone GaInP/GaAs tandem cells. Nevertheless, losses in Jsc and Voc caused by the bonding process, account for less than 10%. AlGaAs single junction cells, designed to be bonded on a silicon cell for low concentrator photovoltaics (LCPV), were also manufactured reaching an efficiency of 15.9% under one sun AM1.5G spectrum for a 2cm2 cell.

The electrical behavior of wafer bonded heterojunctions is usually modeled with the assumption of a pure thermionic conduction at the interface. In this paper, we study the case of highly doped bonded wafers using a Technology Computer Aided Designed (TCAD) modeling approach. Several plausible options of interface including fixed surface charges, interface states densities or a defective interface layer, are discussed and compared with current-voltage measurements. Considering both thermionic and tunnel transport through the interface, we show how the ratio of the competing transport mechanisms depends on the shape of the interfacial energy barrier. Finally, the simulation accurately predicts the effect of the operating temperature on current-voltage characteristics, thanks to a process-compliant description of the direct bonded heterojunction. (C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

We report on ultrascaled (L-G = 23 nm) compressively strained SiGe-based FDSOI pMOSFET with ultrathin body. The devices have been fabricated using a high-K metal gate (TiN/HfSiON) process flow. SiGe channels (3.4 nm) have been epitaxially grown on 3-nm thick 300-mm SOI wafers and combined with embedded Si0.7Ge0.3(:B) raised source and drain (RSD) for Vth, p tuning and smart strain management. In-depth electrical characterizations point out the +120-mV Vth, p tuning, the excellent short-channel, and DIBL control (similar to SOI reference), and show for the first time extremely low variability for SiGe-based FD pMOSFETs. Furthermore, we investigate hole-transport properties as a function of gate length and temperature and demonstrate 60% R-access reduction with SiGe RSD and +330% mobility enhancement at 23-nm gate length with respect to 7-nm thick SOI reference.

This paper analyzes and models the drain-induced barrier lowering (DIBL) for ultrathin silicon body and ultrathin silicon body and thin buried oxide (UTBB) SOI MOSFETs. The channel depth appears as the primary factor in controlling DIBL when the substrate is in accumulation or inversion, whereas space-charge thickness in the substrate is the dominant parameter when the substrate is depleted. Under substrate depletion condition, UTBB devices lose their low DIBL features due to the increased coupling through the effective insulating layer underneath the transistor channel. The proposed model extending MASTAR equations is in agreement with experimental DIBL.

This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage V T platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct V T options (high- V T , standard- V T , and low- V T ). The multi- V T technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi- VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.

We present TCAD simulations based on advanced mobility modeling including Surface Roughness (SR) and Remote Coulomb Scattering (RCS) effects, quantum correction and short channel effects. From these calibrated models, FDSOI 6T-SRAM cells are simulated and compared to experimental data. The very good agreement achieved between simulations and electrical data on both mobility and electrical figures of merit (device and SRAM) offers major opportunities for predictive design based on TCAD simulations.

We hereby present a non-destructive method for extracting the activation level on boron-doped germanium-on-insulator (GeOI) wafers, with a discussion on the impact of the hole mobility model. This method combines Monte Carlo boron profile simulations with optical Ge layer thickness TGe and electrical sheet resistance Rsh measurements. As B atoms are known not to diffuse in Ge for the usual activation temperatures (<800 °C), we can assume that the as-implanted dopant profile remains unchanged after annealing (no modelling of boron diffusion required). We highlight that the knowledge of the hole mobility dependence on activated impurities concentration in Ge is of paramount importance. Several experimental and theoretical models are available in the literature. After relative validity assessments, all of them have been implemented for extraction and unfortunately yield different values scattered over nearly one decade. Still, the lower-bound concentration 2.7×1019 cm−3 is in the range of the state-of-the-art values for B-implanted crystalline Ge and has proven suitable for functional GeOI pMOSFET demonstration.

Germanium has regained attention in the semiconductor industry for MOSFET application because of the higher mobility of carriers – two times higher mobility for electrons and four times for holes – as compared to silicon. In the opposite of the Silicon, the major issue with Germanium is to limit the n-dopant diffusion. Usual n-dopants (Phosphorus and Arsenic for example) are not electrically activated at an acceptable level without a large diffusion of the doping profile and a substantial dose loss. In this work, we have studied the influence of low energy and dose implant (15KeV to 40KeV @ 8E13 to 1E15at.cm-2) and low temperature anneal (515°C to 600°C) on diffusion, exodiffusion and activation of the phosphorus dopant into Germanium. The annealing steps were made in RTP furnace, the chemical profile and electrically active profiles were extracted by using Secondary-Ion-Mass Spectroscopy (SIMS) and sheet resistance measurement (Rs). To investigate the implantation-induced defects in depth, cross-sectional micrographs were made by using Transmission Electron Microscopy (TEM). Experimental results show that we achieved an efficient activation level by tuning both dose implant and anneal temperature, limiting the exodiffusion with pratically no diffusion of the dopant. We also show that very abrupt profile can be achieved with appropriate implant and thermal annealing conditions. To limit the leakage current in devices, we suppose we have to limit the defects generated during the implantation. Specially for dopant activation temperature anneal below 550°C, we have shown and observed by cross-sectional micrograph that the defects are totally removed by addition of a pre step of annealing at 400°C.