Insulating materials used for the packaging of integrated circuits play an important role in the electrical performance of the new System-in-Package (SiP), designed to support flows greater than 10 Gbits/s. These insulating materials must have a low relative permittivity and low dielectric losses up to several tens of GHz in order to insure the integrity of the propagated signals. In this paper the in-situ characterization of molding resins and core materials, used respectively for the encapsulation and the package substrate of chips of new 3D SiP on Board (SiPoB 3D), is carried out up to 100 GHz. These characterizations are performed after the manufacturing process (deposition, drying) of insulators and in their final conditions of use (thicknesses of a few microns, thinning, polishing) since their permittivity is highly dependent on the entire process. The characterization methodology is based on two original techniques: the analysis of the signal propagation on specially optimized CPW lines (coplanar lines) and the analysis of the reflection coefficient measured at the end of a CPW RF probe directly set down the surface of the insulator sample. This new technique makes it possible to overcome whole metallization steps required to achieve waveguide structures used in most material characterization techniques. In addition, the complex permittivity can be 2D-scanned on the entire surface area of the sample of material under test with our technique.

This article focuses on the electrical performance of a new Ethernet contact with four differential pairs called "Octomax." The eight pins of the contact are inserted in a section of 17 mm(2). Such a high-speed interconnect solution is specially developed to operate at 10 Gbits/s in harsh environments for military and aerospace applications. The theoretical study up to 1 GHz enables quantifying the crosstalk between two differential pairs [near-end crosstalk (NEXT)], the return loss (RL), and the insertion loss (IL). An optimization using a combined 2-D-3-D electromagnetic approach, which is simultaneously validated by measurement in frequency and time domains, leads to a final prototype that meets the category 6A Ethernet standard for a predictable data rate of 10 Gbits/s.

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L’archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d’enseignement et de recherche français ou étrangers, des laboratoires publics ou privés. ”Characterization in a Wide Frequency Range (40 MHz 67 GHz) of a KTa0.65Nb0.35O3 Thin Film for Tunable Applications” Grégory Houzet, Thierry Lacrevaz, Cédric Bermond, Bernard Flechet, Arnaud Le Febvrier, Stéphanie Deputier, Maryline Guilloux-Viry, Patrick Quéffélec

Connectors play an essential role in the overall performance of analog and digital electronic systems. Designs, modelling and characterization results of new Ethernet contacts with four differential pairs, named "Ethernet #8"and offering very large bandwidth, are presented. Objectives are to reach data rates of 10 Gbits/s for this contact, expected to be installed on connectors cavities used in harsh environments as military or aerospace industry. A first contact prototype is described and modeled using combined 2D-3D electromagnetic approaches. Return loss, insertion loss and crosstalk between differential pairs, as NEXT loss, are analyzed up to 1 GHz. Finally, an optimization of the contact is performed and a new prototype contact is proposed responding to the category 6A Ethernet standard.

This work aims at providing a RLCG modeling and performance optimization of Redistribution Layer (RDL) in a non-HR substrate up to 67 GHz. Similarly to TSVs, RDL modeling can not be assessed by standard parasitic extraction CAD tools. Therefore, we present complementary measurement and electromagnetic (EM) finite element simulation approaches to provide an accurate modeling over frequency. Firstly, RLCG modeling is developed based on two-port 10 mu m and 20 mu m width RDL test structures at the back-side of a silicon interposer. All measurements show good agreement with simulations. A Pareto diagram is presented quantifying key process and design parameters for standard RDL technology. Secondly, the impact of the EM configuration is evaluated through several 3D EM scenarios including the role of substrate, TSVs ground and interposer BEOL. Finally, as a way of improvement, miniaturization is proposed with a high density 1 mu m RDL on a 10 mu m thick substrate.

A wide band (1 GHz-67 GHz) characterization method of insulator layers is presented. This method is well suitable for a fast, simple and accurate extraction of permittivity of insulators used in interconnects networks. Concerning losses, reto-simulations must be achieved to extract the loss tangent, due to the fact that the extraction of G/(C.ω) includes extrinsic effects. So both lossless and loss cases will be discussed. This non-destructive method and low-cost method presents strong advantages because no specific device under test, no metallic deposit and no etching are required. Measurements are performed using a coplanar GSG RF microprobe directly set down on the dielectric material to characterize.

High speed 3D interconnects are a key element in 2.5D interposer technology that is widely investigated for high performance applications. A wide-band electrical modeling and optimization method of the photonic interposer interconnect chains is presented using scalable models developed based on electromagnetic simulations. Resulting models enable fast and accurate assessment of the whole-chain performances for various sets of technology and design parameters. Using these tools, transmission of 100-Gbps signal through Back-end-of-Line (BEOL), Through Silicon Via (TSV) and Redistribution Layer (RDL) chains are improved following two different methods: independent optimization of each interconnect and optimization of the whole chain. Both techniques are compared for TSV-RDL chain case with wide-range parameter variation and for BEOL-TSV-RDL path satisfying design and technology constraints. Optimization results are validated through comparison with 3D-EM simulation, demonstrating the efficiency of proposed methods to optimize the entire 3D-chain. Results would lead to further works including eye-diagram opening and power consumption optimization, geometrical discontinuity modeling and optimized chain integration.

The feasibility of cointegration of new capacitors, named “through silicon capacitors” (TSCs) with “through silicon vias” in silicon interposers has recently been demonstrated. Two architectures of TSC are extensively investigated in this paper: “axial TSC” whose electrodes are connected on either sides of the silicon interposer and “radial TSC” with electrodes both connected to the metal layers of the back end of line. A general modeling method based on distributed cell segmentation is proposed for both architectures. Validation is performed by measurements from 1 kHz to 40 GHz (above the resonance frequency of the components). A comparative study between radial and axial architectures is performed, leading to the prediction of the performances of those new components. Finally, design rules are established for future integration for power delivery networks decoupling applications.

The continuous requirement of higher communication bandwidths in data centers or high performance computers drives the convergence between ASICs and optical I/Os. Combining 3D integration and Si-photonic technologies on a photonic interposer platform would offer tremendous opportunities for performance improvement assuming that 3D electrical paths are efficiently managed. Routing strategies for die-to-die and die-to-substrate interconnect paths in a photonic interposer are studied through RF modelling of 3D interconnect chains. Wide-band models, extracted from 3D electromagnetic simulations for each elementary 3D interconnect section are cascaded in order to compare the performances of interconnect networks used in the photonic interposer. Transmission losses up to 100 GHz are estimated in frequency domain for differential propagation modes. Next, eye-diagrams, delays and rising-times are observed with a 100 Gbps PAM-2 digital signal for several routing paths. Results led to the identification of critical interconnect sections and the establishment of design tools to optimize the routing paths in photonic interposer architectures.

The «Through Silicon Vias» technology, developed for silicon interposer interconnects network, has inspired new capacitors components named «Through Silicon Capacitors (TSC)». Two architectures of TSC are studied in this paper: the Single Sided-TSC architecture where the TSC bodies are connected in parallel by the BEOL metal layers M1 and M2 and the Double Sided-TSC architecture where the TSC bodies are connected in parallel by using the front side and the back side of the silicon interposer. Modeling methods based on a segmented approach are presented for each architecture. Measurements on a large frequency range (100 Hz–40 GHz) are performed on prototypes of the SS-TSC architecture and the results allow to validate the corresponding modeling method. Next, a comparative study of those two architectures is performed, based on several criteria such as parasitic inductive and resistive components, resonance frequency.