In this paper, we present the latest 22FDX Ⓡ 5G power amplifier (PA) performance enhancement based on a new PA device, EDMOS. A 2-stage PA measured at 22. 9dBm Pout and 33% peak PAE with EDMOS as core device at PA stage. EDMOS achieves 20% higher voltage handling than the popular reference SLVT devices used in 22FDX Ⓡ 5G PA design [1], while not sacrificing the device on-resistance ($\mathrm{R}_{\mathrm{O}\mathrm{N}}$). The cut-off frequency ($\mathrm{f}_{\mathrm{T}}$) and maximum oscillation frequency ($\mathrm{f}_{\mathrm{M}\mathrm{A}\mathrm{X}}$) are 281 GHz and 389 GHz, respectively, which is suitable for 5G PA applications. For Common-Source ($\mathrm{C}_{\mathrm{S}}$) device, EVM measurement is also showing $\sim$25% improvement over the reference SLVT device. The Pout and PAE of 2-stage PA are achieving a new record in the 22FDX Ⓡ CMOS based PA design, which makes this device as a strong candidate for 5GmmW (millimeter wave) PA in handset as well customer premises equipment (CPE).

This paper presents 22FDSOI device RF performance figure of merit dependencies on the design parameters, such as gate length, width per finger, number of fingers, centerline poly pitch, as well as the vertical gate repetition. With a proper design parameters combination, the device can achieve as high as 413 GHz of $f_{MAX}$. As a circuit demonstration, a 2-stage 2-stack power amplifier achieves an output power of 20.2 dBm and 32 % peak PAE at 28 GHz.

This paper proposes three methods of reducing device gate resistance and parasitic capacitance while boosting transconductance of MOSFET on 22FDX®. The fMAX can be improved by 50% and up to 75% for NFET and PFET with respect to a standard 2.0µm finger width layout, respectively.

We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility.

We report on ultrascaled (L-G = 23 nm) compressively strained SiGe-based FDSOI pMOSFET with ultrathin body. The devices have been fabricated using a high-K metal gate (TiN/HfSiON) process flow. SiGe channels (3.4 nm) have been epitaxially grown on 3-nm thick 300-mm SOI wafers and combined with embedded Si0.7Ge0.3(:B) raised source and drain (RSD) for Vth, p tuning and smart strain management. In-depth electrical characterizations point out the +120-mV Vth, p tuning, the excellent short-channel, and DIBL control (similar to SOI reference), and show for the first time extremely low variability for SiGe-based FD pMOSFETs. Furthermore, we investigate hole-transport properties as a function of gate length and temperature and demonstrate 60% R-access reduction with SiGe RSD and +330% mobility enhancement at 23-nm gate length with respect to 7-nm thick SOI reference.

In this paper, an in-depth variability analysis, i.e., from the threshold voltage VT of metal-oxide-semiconductor field-effect-transistors (MOSFETs) to the static noise margin (SNM) of static random-access memory (SRAM) cells, is presented in fully depleted silicon-on-insulator (FDSOI) technology. The local VT variability σ(V)T lower than A(V)T = 1.4 mV · μm is demonstrated. We investigated how this good VT variability is reported on the SNM fluctuations σSNM at the SRAM circuit level. It is found experimentally that σSNM is correlated directly to the σ(V)T of SRAM transistors without any impact of the mean SNM value. The contributions of the individual MOSFETs in the SRAM cells have been determined quantitatively by using a homemade Simulation Program with Integrated Circuit Emphasis compact model calibrated on our FDSOI electrical characteristics. The VT variability in n-channel MOSFETs (nMOSFETs) is more critical than that in p-channel MOSFETs for SNM fluctuations, and σ(V)T in drive nMOSFETs is the key parameter to control for minimizing σSNM.

We present TCAD simulations based on advanced mobility modeling including Surface Roughness (SR) and Remote Coulomb Scattering (RCS) effects, quantum correction and short channel effects. From these calibrated models, FDSOI 6T-SRAM cells are simulated and compared to experimental data. The very good agreement achieved between simulations and electrical data on both mobility and electrical figures of merit (device and SRAM) offers major opportunities for predictive design based on TCAD simulations.