This work aims to evaluate the impact of the presence of a single dopant atom position in the channel region on the on-current variability of SOI Gate-All-Around (GAA) nanosheet transistors using an in-house quantum-corrected Monte Carlo simulator. Devices with different nanosheet heights and widths are considered. The simulation results showed that the device dimensions and the dopant's position influence the on-current's variability, with up to 39.71% of relative deviation of the electric current, which occurs when the dopant is placed in the center of the cross-section 10 nm away from the source of a GAA nanosheet transistor with channel length of 40 nm, fin width of 10 nm and fin height of 5 nm.

This work presents an experimental assessment of self-heating in SOI nanowire MOSFETs in ambient temperatures ranging from 300 K down to 4.2 K using the gate resistance thermometry technique. The temperature increase in the channel region is extracted, and the differential thermal resistance is obtained and plotted as a function of the device temperature. Despite the lower power dissipated by a single nanowire, the operation temperature decrease causes the temperature rise in the channel to increase from around 6 K at room temperature up to 53 K in the cryogenic range. The thermal resistance is considerably lower in nanowires than in widechannel devices, although both types of transistors present an abrupt increase in the differential thermal resistance at extremely low device temperatures.

In this study, an experimental assessment of transport parameters in 7-level stacked nanosheet GAA nMOSFETs is conducted, employing the Y-Function methodology to extract carrier mobility. Specifically, the contribution of horizontal and vertical conduction planes to mobility and degradation factors is investigated for transistors with varying channel lengths and nanosheet widths. The findings reveal that while overall low-field mobility demonstrates weak dependency on nanosheet width, it suffers some reduction in short-channel transistors. Furthermore, the mobility degradation was analyzed, and the results indicate that overall mobility degradation coefficients depend on the nanosheet width, as the balance between horizontal and vertical contributions varies. Notably, while the linear degradation factor dominates the mobility degradation at horizontal planes, vertical planes exhibit a dominant quadratic degradation factor. This suggests larger surface roughness scattering at sidewalls compared to horizontal planes.

This work aims to evaluate the impact of a single dopant position in the channel on the on-current of nanowire MOS transistors through atomistic simulations. The dopant was placed in 27 different positions along the silicon layer, and the device was biased with different gate voltages and a drain voltage of 0.9 V. The results of the atomistic simulations show that the dopant in the middle of the cross-section near the source-channel interface has the highest impact on the oncurrent, with a reduction of 33.11% in comparison with a device without any dopant in the channel, operating at VGS of 0.4 V.

This paper presents three-dimensional TCAD simulations of n-type nanowire MOSFET operating from room temperature down to 40 K. The simulator models' parameters were calibrated considering mobility scattering mechanisms from 300 K down to 82 K, and their results are compared with experimental data. Gaussian interface traps are considered in order to fit the effects of Coulomb scattering. A good agreement between the simulated and experimental transconductance and drain current as a function of gate voltage curves, from 300 K to 82 K, was obtained. The TCAD simulations also described the threshold voltage increase with temperature, and a well-defined Zero Temperature Coefficient point down to 40K.

Experimental results of analog parameters of nMOSFETs fabricated in a 180 nm commercial CMOS technology, with different channel lengths, operating at temperatures ranging from 300 K down to 93 K, are presented and discussed in this paper. The transconductance-to-current ($\mathrm{g}_{\mathrm{m}}/\mathrm{I}_{\text{DS}}$) ratio, Early voltage ($\mathrm{V}_{\text{EA}}$), and intrinsic voltage gain (Av) were analyzed.

This work presents an experimental evaluation of the influence of the extraction method on the analysis of threshold voltage variability in nanosheet transistors, using seven drain current-based methods. SOI The experimental results of nanosheet transistors with different fin widths and channel lengths show that the choice of the extraction method might change not only the threshold voltage mean value but also its relative deviation.

This article investigates the impact of random dopant fluctuation (RDF) on the current of a n-type nanowire silicon on insulator (SOI) triple-gate transistor. This study was performed employing a quantum-corrected Monte Carlo (MC) device simulator that was successfully assessed by comparing the simulation characteristics curves with experimental data. The results demonstrate that the impact of a single dopant atom on the transistor's current depends on the dopant position along the channel length, fin height, and width. A random dopant in the channel affects the electrostatics, the electron density, and the electron mobility, thus degrading the transistor current. The study was performed for V-GS = 0.5 V, and V-DS = 0.2 V, V-DS = 0.5 V, and V-DS = 0.7 V. For V-DS = 0.2 V, the maximum current variation was observed when the single dopant is placed in the middle of the channel length and the middle of fin height and width. For this case, the variation is 19.47% with respect to the nominal current. For V-DS = 0.5 V and V-DS = 0.7 V, the maximum current variation was observed when the dopant is closer to the source region, and the current variation is, respectively, 20.60% and 21.48%.

This paper evaluates the electrical characteristics of Inversion-mode (IM) and Junctionless (JNT) SOI nanowire MOSFETs across a temperature spectrum from 300K to 82K. The study examines devices with varying fin widths, utilizing experimental data to analyze crucial electrical metrics, including threshold voltage, inverse subthreshold slope, and carrier mobility throughout the temperature range. The investigation also explores how these parameters are influenced by channel length and fin width.

This study assesses the analog parameters of 7-level stacked SOI nanosheet transistors. The impact of nanosheet width, channel length, and bias condition is thoroughly examined through the analysis of experimental data. Key parameters, including transconductance, output conductance, and intrinsic voltage gain, are used as figures of merit for this investigation. A comparative analysis with data available in the literature reveals that the intrinsic voltage gain exhibits less sensitivity to nanosheet width when compared to single-level and 2-level stacked nanosheets.

This paper investigates the separation of the drain current components in top-bottom and sidewall currents, and the extraction of their respective low-field mobility in two-level stacked nanowire nMOSFETs. The study presents a detailed analysis of carrier transport in different crystallographic planes, emphasizing the anisotropy in mobility due to variations in sidewall roughness induced by the etching process. Devices with variable fin widths (WFIN) were measured. The effective mobility and the mobility degradation factors were extracted using the Y -function method. This study provides insights into the optimization of process and device modeling for stacked nanowire MOSFETs.

This study investigates commercially available 180 nm CMOS devices under deep cryogenic conditions, focusing on both short (180 nm) and long (600 nm) channel nMOS devices at temperatures down to 3.2 K. We meticulously measured key parameters including threshold voltage (V-th), carrier mobility (mu n), subthreshold slope (SS), on-current (I-on), and off-current (I-off). Notably, as temperatures decreased, V-th, I-off, and SS values declined, while I-on and mu(n) exhibited an increase. A notable observation was the dual Z(t) values for the short channel device, aligning with the significant rise in series resistance post carrier freeze-out at 77 K. Our results provide a foundational understanding for the extraction of compact model parameters, crucial for cryogenic CMOS simulation and circuit design. For short channel devices, Vth evolved from 0.6 V at room temperature to 0.85 V at 3.8 K, carrier mobility increased from 200 to 400 cm(2)/V(2)s, and SS improved from 90 mV/dec to 20 mV/dec. Conversely, long channel devices, measured from 113 K to 3.2 K, showed V-th alteration from 0.60 V to 0.64 V, mobility enhancement from 833 to 1220 cm(2)/V(2)s, and SS improvement from 30 mV/dec to 10 mV/dec.

This paper outlines a technique for measuring the temperature rise in a nanowire SOI MOSFET, caused by the self-heating effect, utilizing a parallel gated PIN diode. The analysis is conducted through electrothermal 3D TCAD simulations across an environment temperature range of 300K to 600K. Additionally, the impact of the separation distance between the nanowire MOSFET and the PIN diode is thoroughly examined.

This work presents an analytical model for the drain and gate currents of silicon nanowire and nanosheet MOS transistors valid in all operating regions in the temperature range from 300 to 500 K. Analytical models for the tunneling components as well as for the reversely biased drain-to-channel PN junction are presented. Also, the models accounting for the necessary modifications in the silicon physical quantities for high-temperature operation, such as the maximum carrier mobility, the bandgap, and the intrinsic carrier concentration, are presented. The proposed model uses a single set of parameters, extracted at room temperature, to describe the high-temperature operation of silicon nanowire MOSFETs. The model is validated with comparisons between modeled and experimental results for devices with different fin widths and operating temperatures, with good agreement.

This article aims to present experimental results of nMOSFETs from a 180 nm commercial CMOS technology, with different channel lengths, operating at temperatures ranging from 80 K to 300 K. The source-drain resistance $(\mathbf{R}_{\mathbf{SD}})$ , threshold voltage $(\mathbf{V}_{\mathbf{TH}})$ , subthreshold slope (SS), low-field mobility $(\boldsymbol{\mu}_{\mathbf{0}})$ , and the linear $(\boldsymbol{\theta}_{\mathbf{1}})$ and quadratic $(\boldsymbol{\theta}_{\mathbf{2}})$ mobility degradation factors were extracted. The extraction of $\mathbf{R}_{\mathbf{SD}}$ yielded an average value of $\mathbf{61.90} \pm \mathbf{3.83}\ \mathbf{\Omega}$ all devices and temperatures. Comparing all the devices, as the temperature decreased, $\mathbf{V}_{\mathbf{TH}}$ showed an increase in its value between 22.3 % and 33.9 %; SS showed a decrease between 59.7 % and 62.1 % of its value; $\boldsymbol{\mu}_{\mathbf{0}}$ increased 162.4 % for the shorter device and 243.2 % for the longer device; $\boldsymbol{\theta}_{\mathbf{1}}$ varied less for longer devices; and $\boldsymbol{\theta}_{\mathbf{2}}$ showed more variations in its values, being less intense in shorter devices. Analyzing the channel shortening, the rate of change $\mathbf{dV}_{\mathbf{TH}}/\mathbf{dT}$ showed, in magnitude, a decrease from 0.696 mV/K to 0.561 mV/K, the rate of change dSS/dT showed an increase from $\mathbf{0.197}\ \mathbf{mV} /(\mathbf{dec} \cdot \mathbf{~K})$ to $\mathbf{0.223}\ \mathbf{mV}/(\mathbf{dec}\cdot \mathbf{K})$ , and the ZTC was from 0.67 V to 0.77 V.

This study explores the carrier mobility and its degradation factors in relation to temperature for 2-level stacked nanowire MOSFETs within the temperature range of 100 K to 400 K. The low-field carrier mobility and its degradation factors were extracted using the Y-function. Additionally, it was observed that the peak transconductance is achieved at a higher overdrive voltage (VG-VTH), particularly as the temperature decreases. Notably, the low-field mobility is more sensitive in wider devices. Compared to other technologies such as omega-gate nanowires and planar fully depleted SOI transistors, this technology exhibits less sensitivity of low-field mobility to temperature variations. The first-order degradation factor was observed to decrease with rising temperature, while the second-order factor exhibited an increase within the same temperature range. The variation in the first and second order degradation factors with temperature is more pronounced in wider devices.

This paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths and fin widths were measured. The results show that temperature rise increases the GIDL current for stacked nanowire transistors and its dependence on nanowire width. For a fixed gate voltage, the channel length reduction increases the GIDL current except in the presence of short-channel length. Three-dimensional TCAD simulations were performed, and the band-to-band generation was extracted for devices with different channel lengths, widths, and temperatures. The temperature rise increases valence and conduction energy levels, being more pronounced in the first, which causes the reduction of the lateral distance between the two levels, finally favoring the transversal band-to-band tunneling.

This work aims to perform a comprehensive comparison of the electrical properties of junctionless and inversion-mode nanowires MOSFETS, fabricated with similar gate stack and state-of-art process, in the temperature range from 300 K to 580 K. The comparative analysis is performed through the main electrical parameters of the devices, such as the threshold voltage, subthreshold current and slope, DIBL, conduction current, mobility, and maximum transconductance extracted from experimental data. Devices with different fin widths are compared. It is demonstrated that the inversion-mode nanowire transistors present higher performance with three times higher maximum transconductance and conduction current and twice higher low field mobility than the junctionless’ with a fin width of 10 nm at a fixed temperature. On the other hand, the junctionless nanowire transistors presented higher thermal stability of their electrical parameters with a 75% lower variation of maximum transconductance with temperature, 77% lower maximum transconductance variation with temperature, and 22% lower temperature coefficient of mobility.

This work presents a TCAD-based performance evaluation of ultra-thin body and box (UTBB) Silicon-On-Insulator (SOI) junctionless (JL) ion sensitive field effect transistor (ISFET) operating in dual-gate mode. The dual-gate operation allows to take advantage of the increased sensitivity from the SOI capacitance coupling and overcome the Nernstian limit. The threshold voltage (V Th ) and drain current (I DS ) sensitivities to the pH are analyzed. The V Th sensitivity showed gains up to 109.5 and I DS sensitivity increases up to 404.5% compared to single gate mode.

In this work, an experimental evaluation of Gate-Induce Drain Leakage (GIDL) current is presented for nanowire and nanosheet-based SOI transistors. The effects of fin width and temperature increase are studied. Obtained results indicate that the increase in device width makes the GIDL current more sensitive to temperature increase. Three-dimensional numerical simulations have shown that despite the reverse junction leakage increase with temperature, leakage current in nanosheet and nanowire transistors is composed predominantly of GIDL current. The change in valence and conduction bands caused by temperature increase favors the band-to-band tunneling, which is responsible for the worsening of GIDL at high temperatures.