The Y-shaped two-way and four-way Wideband Power Divider (WPD) that can encompass X-band, Ku-band, and ultra-wideband (UWB) is proposed in this letter. Bridging resistors and triangular tapered microstrip line (TTML) are used in the design of the suggested power divider, which is constructed on a low-loss Rogers RT-5880 substrate. Utilizing a corporate feeding network of a 2-way wideband power divider (2WBPD), the Y-shaped 4-way wideband power divider (4WBPD) provides measured insertion loss between -6.16 dB and -14 dB, measured isolation below -16 dB, measured input return loss below -10 dB, and measured output return loss below -10.6 dB in the 2.89 GHz to 18 GHz band. The measured amplitude imbalance is within ±0.13, and the phase difference ranges from 17.2° to -32.03° between output ports. Applications for these wideband power dividers include multistage amplifiers and feeding networks in antenna arrays.
his study expands the understanding of how drain voltage and temperature impact the Negative Bias Temperature Instability (NBTI) effect in Junctionless Nanowire Transistors (JNTs). The electric field within the channel, which is crucial for NBTI, is affected by variations in the voltage between source and drain (VDS), thereby influencing the behavior of space charges. This study demonstrates that the operating regime (induced by the VDS and the temperature) has a significant influence on the variation of the VTH. The results show that the threshold voltage shift (ΔVTH) initially increases with temperature due to its influence on the Fermi potential and flatband voltage. However, beyond 340 K, ΔVTH tends to stabilize or slightly decrease as the device operates closer to the accumulation regime under constant bias conditions. For heavily doped devices, an increase in temperature tends to have little effect on charge mobility, which may ultimately explain the reduced temperature dependence of NBTI observed in JNT devices. This temperature-dependent transition highlights that the NBTI response of JNTs is strongly influenced by the operating regime and bias conditions adopted in this study.
This work examines how device scaling influences the thermal noise performances of InAsxSb1-x n-channel ultra-thin body metal oxide semiconductor (UTB-MOS) for varied lengths of channel, thicknesses of channel, and thicknesses of insulating layer for varying both the gate voltages and the frequencies. To validate the current model, the simulated gate transfer characteristics graph is compared with published experimental results. Based on transconductance (gm) and drain current (ID) simulation results, minimum noise figure (NFmin) , noise resistance (Rn), and the drain current noise spectral density (SID/ID²) were determined. According to our findings, thermal noise in InAsxSb1-x n-channel MOSFETs is dependent on device parameters and can be reduced via suitable device scaling the length of the channel, thickness of channel and thickness of insulator. When the channel length was decremented from 0.1 µm to 0.04 µm at 1V of gate voltage a 0.75 kΩ decrement in noise resistance is achieved . The channel length decrement also yields a power spectral density of roughly 2.2×10⁻²⁴ Hz⁻¹ and a minimum noise figure of roughly 1.3dB .Further improvements were observed with a reduction in channel thickness. Specifically, noise resistance and power spectral density values are significantly lowered when the channel thickness was decreased from 0.1 µm to 0.04 µm at the same gate voltage. A comparative study of the Noise conductance and Input referred noise with respect to frequency for different channel thickness and insulator thickness are calculated and found that the values of Noise conductance and Input referred noise decreases with increment in channel thickness and insulator thickness.
Global arable land shrinks due to rising population pressures, traditional soil-based farming becomes increasingly challenging. To address this, the project aims to design an automatic hydroponic system that operates independently of external climate conditions. This system is capable of growing common crops, indoors for food production. After assessing numerous hydroponic systems for automation compatibility, the ESP 32 microcontroller was selected as the core processing unit, interfacing with many sensors, including as pH, TDS, and DHT11, to enhance system parameters with minimum human oversight. The system utilizes a cloud based IoT platform to monitor, store, and display real-time data for remote access. It ensures optimal plant growth conditions, providing notifications and system status updates. This platform not only supports plant researchers by offering crucial data on system factors affecting plant growth but also aids in enhancing indoor and outdoor farming practices. With automation in place, the system reduces labour-intensive tasks and helps us to make informed decisions by analysing the large amount of data, collected from the different sensors used. Analysis of the results indicates that the automated hydroponic system presents a well-integrated design encompassing both testing and implementation phases. The system demonstrates effective regulation of water and nutrient delivery, while continuously monitoring ambient environmental parameters to support optimal plant growth conditions. Finally, it allows us for growing summer vegetables year-round, regardless of outside weather conditions.
The continuous scaling of CMOS technology has highlighted significant challenges in power consumption and energy efficiency, particularly in arithmetic units of digital systems. This paper presents a novel adiabatic arithmetic unit based on the Junctionless Double-Gate MOSFET (JLDGMOSFET), aiming to minimize power dissipation and enhance energy efficiency. The proposed structure leverages the unique characteristics of the JLDGMOSFET to support adiabatic switching, substantially reducing both leakage power and energy consumption in the subthreshold regime. The proposed adiabatic adder is simulated using SILVACO ATLAS, and its performance is compared against conventional static CMOS adiabatic adders in terms of power dissipation and delay and Power Delay Product (PDP). Simulation results show that the JLDGMOSFET-based arithmetic unit achieves a Power-Delay Product (PDP) reduction of over 85% and a power consumption decrease of up to 90% across a range of supply voltages (0.14 V to 0.30 V), as compared to conventional counterparts. These improvements validate the effectiveness of integrating junctionless device technology with adiabatic logic principles for ultra-low-power arithmetic applications. The proposed approach is particularly suitable for energy-constrained environments such as IoT and biomedical devices, where power efficiency is of paramount importance.
Quantum conversion efficiency and fill factor of single quantum well solar cell are analytically investigated for lower doping concentration in the well region considering the effects of SRH recombination, Auger recombination and radiative recombination. Poisson’s equation is solved at the interface junction to obtain open-circuit voltage and short-circuit current under optimized well layer thickness, where material consideration leads to type-I heterostructure for better quantum confinement. Comparative analysis exhibits better performance of 0.6% - 13.64% efficiency even when MQW structure is considered; and further little enhancement is obtained when compared with DBR based MQW structure having similar structural configuration under equal biasing condition. Extremely insignificant recombination coefficients for Auger, radiative and SRH are obtained which together speaks for higher quantum efficiency of the device in the applied voltage range of interest, and therefore, established novelty of the proposed device. Henceforth, in view of size and complexity also, the present optimized device dimension leads to higher outcome, as obtained using SCAPS-1D software.
As device dimensions continue to scale down into the nanometer regime, the impact of statistical variations on device parameters becomes increasingly critical, particularly for junctionlessultra-short channel MOSFETs. This paper investigates the influence of process-induced statistical variations—such as channel length, gate oxide thickness, doping concentration, and gate work function—on the threshold voltage characteristics of these advanced devices. Using 2D/3D TCAD simulations, we analyze the sensitivity of threshold voltage to individual and combined parameter fluctuations. The results reveal that even slight variations can lead to significant deviations in device performance, contributing to increased variability and reduced reliability in integrated circuits. The study underscores the necessity of incorporating variability-aware design approaches and enhanced process control in future nanoscale CMOS technologies. The findings provide critical insights for optimizing the design and manufacturing of robust, energy-efficient, and high-performance junctionless MOSFETs suitable for next-generation electronics.
Every day the reduction of dimensions of semiconductor material based devices to achieve nanometers scale, consequent improvement in energy consumption becomes more prominent in VLSI domain. A promising nanoscale technology Quantum-dot Cellular Automata (QCA) takes advantage of the electron tunneling between quantum dots within a cell as well as the electrostatic interaction between dots in adjacent cells. QCA technology outperforms conventional complementary metal-oxide semiconductor (CMOS) technology in terms of speed, power consumption, and area utilization. Achieving logically and physically reversible QCA circuit development can lead to remarkable energy dissipation reductions. The multiplexer and full adders are crucial components of the arithmetic logic unit (ALU), which is a basic part of the central processing unit of a processor that performs arithmetic and logical operations. In this brief, we present a new special low complexity QCA 4:1 multiplexer that is application-specific to the proposed ALU, based on the extracted features of the ALU's arithmetic operations. Additionally, a novel QCA full adder that takes into account cell reduction is suggested. Similarly, our validated proposed structures, a coplanar QCA based ALU structure is constructed to perform eight arithmetic and four logical operations. The QCADesigner tool assesses the suggested structures' functional soundness. Our proposed design shows improvement in terms of cell number, area, cost and power consumption compared to counterparts design of previous researchers.
A common-mode compensation technique (CMCT) is proposed for a 10-bit differential synchronous SAR ADC implemented in 28nm CMOS technology. The switching scheme improves upon the conventional monotonic procedure by reducing the number of required reference voltagesand minimizing power consumption through reduced total capacitance. It eliminates input common-mode variation and the associated nonlinear shift in comparator offset, requiring only minor modifications to the DAC control logic without increasing the total capacitance. Theoretically, it achieves the same energy efficiency during the comparison phase as the VCM-based scheme, while incurring additional energy during the reset phase. Post-layout transient noise simulations at the typical corner showed an effective number of bits (ENOB) of 9.82 at the maximum sampling rate with a Nyquist input, using the technique only for the three most significant bits. Total power consumption was 510 µW. Static measurements reported a differential non-linearity (DNL) of +0.16/–0.23 LSB and an integral non-linearity (INL) of ±0.4 LSB. The resulting figure of merit (FoM) was 56.55 fJ/conversion. Additional corner and Monte Carlo simulations confirmed robust performance across PVT and mismatch variations.
As the demand for video transmission surges in remote work, education, and streaming services, the need for continuous advancements in video encoding technologies becomes increasingly evident. Adapting to the evolving demands of efficient video delivery and consumption requires continuous advancement and refinement of video encoding standards. In this scenario, the Versatile Video Coding (VVC) stands out as a leading example, representing the current state-of-the-art in video coding. This work presents a Machine Learning (ML) approach to accelerate one of the novel tools within the VVC: the Affine Motion Estimation (AME). AME is part of the VVC Inter-Frame Prediction, and it is one of the most computationally intensive tools within VVC. The hardware-friendly Decision Tree ML method was explored in this work to accelerate the AME. A total of 12 Decision Trees were trained to determine whether to skip or not to skip the AME for each block size supported by AME in VVC. The proposed approach achieved an average reduction of 5.54% in the total VVC encoding time and an average reduction of 63.20% in the AME execution time, resulting in an average BD-BR efficiency loss of only 0.50%. These results demonstrate that the strategy of using Machine Learning to reduce the computational cost of VVC has the potential to continue yielding significant results in future solutions.
In this paper, an innovative approach has been proposed to design a high dynamic range voltage variable attenuator. The attenuator possesses good attenuation flatness in the desired frequency band from 1.1 GHz to 1.3 GHz. A source-controlled attenuator consists of main transistor and a load transistor in series. Minimum attenuation is achieved due to low control voltage. At high control voltage, the main transistor is off, hence, maximum attenuation occurs. If the gate of load transistor is grounded, then dynamic range reduces. To increase attenuation range, an active network in parallel to the main transistor has been used. The circuit offers good impedance match and low amplitude error and phase error. Hence, the attenuator finds application in beam control.
In this work, the performance parameters of sub-5 nm double-gate (DG) junctionless field-effect transistors (JLFETs) based on monolayer (ML) arsenene (As) and antimonene (Sb) under the influence of gate length (Lg) and doping concentration (Nd) are investigated. The performance measures, including as on-current (Ion), gate capacitance (Cg), subthreshold slope (SS) and transconductance (gm) are analyzed and examined from the Id–Vg characteristics of the simulated As/Sb JLFETs using advanced quantum transport simulations methods. Our results show that both Ion and SS exhibit a linear dependence on Lg and increase with rising Nd, indicating enhanced drive current and switching behavior at higher doping levels. In contrast, the gate capacitance(Cg) initially decreases sharply with increasing gate voltage and then rises in a linear manner, but it is linear with Lg. Whereas, the transconductance (gm) exhibits a linear relationship with gate length (Lg) and increases exponentially with doping concentration (Nd). All these parameters meet the International Technology Roadmap for Semiconductors (ITRS) performance benchmarks projected for 2028, confirming the technological viability of ML As/Sb JLFETs. When compared to their DG ML MOSFET counterparts, the proposed JLFETs demonstrate superior electrical performance, including higher Ion, steeper SS, improved Cg and gm values. These attributes make ML As/Sb JLFETs strong candidates for both high-performance (HP) and low-power (LP) applications in future nanoscale electronic systems. The study establishes ML As and Sb-based JLFETs as promising transistor architectures for next-generation nanoelectronics.
A one input and five outputs biquadratic filter circuit uses one plus-type second-generation current conveyor (CCII), two plus-type differential voltage current conveyors (DVCCs), four grounded resistors and two grounded capacitors is described. The voltage-mode allpass, notch, highpass, bandpass and lowpass filters are available in the proposed circuit, simulta-neously, with high input impedance. The uses of only grounded capacitors and resistors is beneficial for integration. The use of only plus-type current conveyors simplifies the circuit config-uration. Simulation results of the proposed circuit is presented to confirm the theoretical analysis.
In this study, highly oriented pyrolytic graphite (HOPG) samples were exposed to 14 MeV neutrons at fluences up to 1.7x10^10 neutrons/cm^2 to investigate the effects of irradiation-induced disorder on their electrical transport behavior. Atomic force microscopy (AFM) revealed an increase in the average step distance between adjacent planes with neutron fluence, indicating enhanced surface roughness and structural disorder. Electrical measurements performed between 5 K and 300 K showed a systematic decrease in the residual resistivity ratio (RRR) from 9.6 for pristine HOPG to 3.8 for the most irradiated sample, reflecting increased carrier scattering due to lattice defects. Magnetoresistance (MR) measurements revealed an extremely large MR in pristine HOPG, reaching 2.2x10^5% at 5 K and 9 T, which progressively decreased with neutron exposure. The combined morphological and transport analyses demonstrate that neutron irradiation degrades the crystalline quality of HOPG, leading to suppressed electrical conductivity and magnetoresistive response. These findings highlight the correlation between structural disorder and charge-carrier dynamics, providing valuable insight for optimizing graphitebased materials used in high-radiation environments such as the NUMEN experiments. Fast neutron irradiation can strongly affect the structural and transport properties of HOPG, a key material in advanced thermal management and radiation-tolerant systems.
With the increased computing facility powered by cutting edge VLSI technology and new algorithms developed in the domain of Machine Learning (ML), today fast, accurate and realistic equivalent ML models replaces simulations built on the finite element method (FEM). In this paper, various machine learning regression models has been trained with same dataset of semiconductor device, generated from TCAD simulation and is used for device performance prediction. Performance of different regressor models has been compared and grouped into two sections. As device parameters and FoM bear a non-linear relationship, Gradient Boosting and XGBoost regressor models with proper hyperparameter optimization predicts the output much better than other regressor models. This work shows that choice of proper Machine Learning prediction model plays an important role when used as an alternate to TCAD simulation in semiconductor device design.
Impedance Spectroscopy (IS) is a valuable technique for characterizing sensing materials in the frequency domain. However, interpreting IS data and linking them to equivalent circuit models with combined effects can be challenging for beginners in the technique. To address this issue, this work revisits the fundamentals of IS and presents a friendly didactic Virtual Instrument (VI) designed to support students and researchers through intuitive simulation and analysis tools. While similar features exist in well-established research software, our VI takes an educational approach by allowing real-time manipulation of model parameters and immediate visualization of their impact on impedance spectra. The software also performs model fitting to experimental data, with deviations closer to commercial algorithms, and thereby promoting critical analysis of model adequacy and the development of analytical skill. The tool was initially applied with undergraduate research students, demonstrating strong potential for educational use. As a proof of concept, humidity-sensitive MWCNT-based gas sensors were characterized, and fitting results highlighted the most responsive electrical parameters. This approach offers a practical and accessible way to teach IS principles and electrical analysis of materials.
This work presents an analysis of the Low-Frequency Noise (LFN) of Junctionless Nanowire Transistors (JNTs) in different conditions. The analysis was first performed through numerical simulations, validated with experimental data, considering a single interface trap at the center of the device. It is shown that noise increases with drain and gate voltages, except for shorter devices at low drain bias, where the surface potential behavior near the source side significantly influences the noise. In the sequence, an experimental analysis was performed for longer devices, showing that the activation of single trap centers can dominate the overall noise characteristics, especially at higher frequencies and drain biases. This is related to the surface potential variation with device biasing, which is responsible for activating specific traps at the detriment of others.
An alternative approach for through-silicon via (TSV) fabrication was developed using laser drilling, chemical polishing, and TiN deposition by dc magnetron sputtering. The process was optimized by adjusting the laser parameters, and the best results were obtained at a pulse repetition frequency of 1 kHz, where drilling was stable and the via walls exhibited reduced thermal damage. Two laser exposure modes were compared: single-pass and six-pass. The six-pass condition produced smoother surfaces, attributed to a cleaning effect between consecutive irradiations, although an hourglass-shaped profile was observed. Raman spectroscopy confirmed that the laser process did not modify the silicon crystalline structure, while chemical polishing introduced slight compressive stress on the TSV surfaces. TiN films deposited on both wafer sides exhibited continuous and conformal coverage, with an average thickness of 190 nm. Moreover, increasing the wafer thickness to 530 µm resulted in a more cylindrical via geometry, which is advantageous for metallization and 3D interconnect uniformity. The proposed route provides a low-cost and reliable alternative for TSV fabrication, yielding sidewall quality compatible with 3D integration and quantum-computing interconnect applications.
This study presents a detailed exploration of Convolutional Neural Networks (CNNs) for aerial image classification on satellite platforms, leveraging the FINN framework implemented on AMD/Xilinx 7-series APSoCs. By systematically examining the trade-offs between quantization levels, network topologies, and architectural parallelism, we achieved high accuracy for different quantizations, and demonstrated robust performance scaling from 542 FPS to 16.3k FPS. Our results highlight critical design decisions for integrating CNN accelerators with both hardcore ARM Cortex-A9 and softcore NOEL-V RISC-V processors, offering insights into resource utilization, energy efficiency, and system performance. This work provides a valuable roadmap for optimizing in-orbit image processing systems in next-generation satellite applications.
In this article, a two-stage error correction approach is proposed to enhance the accuracy of ultrasonic distance measuring techniques utilized for smart parking systems. The DHT11 monitors environmental conditions, such as temperature and humidity,which greatly influence the accuracy of the sensors, and the HC-SR04 functions as a distance sensor. A two-step correction process is proposed to address these errors. The process is carries out with the use of a 20 15 10 ANN model in the beginning,which which contains a set of novel features for environment changes processing. The results are refined in a second stage by means of statistical correction, mean error correction, and closest mean are two of such techniques.The model performanceis measured by six indicators: global loss, mean squared logarithmic error (MSLE), mean absolute error (MAE), coefficient of determination (R²), root mean square error (RMSE), and relative percent forecast error (RPF). For on-line testing, the proposed framework is installed on a vehicle base. Experimental results show that the measured distance trends are close to real distances with an accuracy of 98.72% . The system is a “greening” solution for smart parking systems as it consumes very little power.
