Design of a highly reliable SPARC-V8 processor for space applications requires consideration singleevent effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose(TID). In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78 9.78 mm2, and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements’ experiments, which show TID resistance to 300 krad(Si), SEL immunity to greater than 92.5 Me V cm2/mg, and an SEU error rate of 2.51 10-4per day.

An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies.

分析SoC高度密集的功能集成和专用性与可编程性相结合的发展趋势以及SoC未来的关键技术,介绍SoC技术在国内外航天领域的应用,并对我国继续开展SoC技术研究提出建议。

This paper describes the architecture and implement of the specific processor,SPARC_-V8FTS,designed for fault tolerant system.The SPARC_-V8FTS integrates duplicate core processor and the Fault-tolerant manager.The core processor is 32-bit micro processor based on the SPARC V8 specification.The Fault-tolerant manager provides the mechanism of error detection,error diagnosis,error recovery from a transient fault,and reconfiguration that makes the SPARC_-V8FTS to a single processor system to run continuously when a permanent fault takes place.SPARC_-V8FTS drastically reduces the hardware count of a system,and performs all the fault tolerant operations.It provides high system reliability with low performance overhead.

This paper describes a 16-bit stereo audio Σ Δ A/D converter. It consists of two identical novel stability fifth-order switched capacitor ΣΔ modulators using dynamic dither scheme, bandgap circuits and a decimation digital filter. A new multistage comb filter was used for the front end decimation filter. The ADC was implemented in 0.5-μm 5-V CMOS technology. The chip die area occupies only 4.1 *2.4mm 2 and dissipates 90mW. © 2005 IEEE.

This paper describes the architecture and implementation of the application specific processor, the NBHAWK, which designed for fault-tolerance. The processor tolerates transient SEU errors. We propose a novel approach: Optimal Odd-weight-column Codes ,to check the transient fault of register-file, which can reduce the penalty of recovering the pipeline. In addition, a lot of efficient techniques are used to improve the reliability of the processor ,such as TMR registers, TMR clock, on-chip EDAC, parity, and forced cache miss. The chip was manufactured on the smic 0.18μm CMOS technology. The radiation-injection tests showed that all of the injected errors (＞ 50,000) were corrected or handled successfully. The 252CF radiation-source, 3.5 u Ci radiation-activity, and 43 MeV.cm2/mg.average LET were used to error-injection.

The paper introduced the controller design of a embedded microprocessor, NPUARM7, which is compatible with ARM7TDMI instructions set. It presented a novel Finited State Machine(FSM) mechanism which was decided by the different sort of instruction. A decoding method step by step controlled by FSM was described. The method simplified the decoding logic circuits, improved the decoding efficiency, and eliminated the bottle-neck in the RISC pipeline. Test shows that this scheme is much suitable for high-speed, low-power and embedded application.

The paper presented a novel computer information security solution scheme by combining software and hard-ware way in order to prevent the potential security risk of computer information which is copied via USB interface, CD-ROM, floppy driver, serial and parallel interface, and network port. The proposed scheme can configure flexibly the functions of all interfaces and close up the interfaces or encrypt the copied information. The PCI bus specifications and encrypting/decryption algorithmic were implemented on a FPGA. The software and the hardware simultaneously worked well and were protected each other. The application result shows the system had highly reliability and guaranteed the computer information’s security well.

This paper describes a 16-bit stereo audio Sigma Delta A/D converter. It consists of two identical novel stability fifth-order switched capacitor Sigma Delta modulators using dynamic dither scheme, bandgap circuits and a decimation digital filter. A new multistage comb filter was used for the front end decimation filter. The ADC was implemented in 0.5-mu m 5-V CMOS technology. The chip die area occupies only 4.1 *2.4mm(2) and dissipates 90mW.

The paper presents a novel lower power polyphase transformable stage non-recursive comb (PTSNC) filter architecture considering the area and power consumption, which is very suitable for high-order oversampled sigma delta A/D converters. The proposed decimation filter has 1/3 less hardware and power compared to conventional non-recursive decimation filters when the filter was implemented using 0.6-mu m CMOS standard when the circuit work clock was 100MHz.

The area, speed and power consumption of oversampled data converters were governed largely by decimation filters in sigma delta A/D converters. The paper presented a design and implementation of a low power and high-speed sigma delta digital decimation filter which it was designed by top-down method. The decimation filter consists of a modified cascaded integrator-comb (CIC) decimation filter and two-stage half-band filter. The proposed CIC filter has 15% less hardware and 53% power saving compared to conventional CIC filters. The filter is implemented using 0.6-/spl mu/m CMOS standard cell and contains 6,560 equivalent gates resulting in a power consumption of only 35 mW from a 5-V supply. The decimation filter is very suitable for high-order sigma delta converters.

This paper describes a 16-bit stereo audio ΣΔA/D converter. It consists of two identical novel stability fifth-order switched capacitor ΣΔ modulators using dynamic dither scheme, bandgap circuits and a decimation digital filter. A new multistage comb filter was used for the front end decimation filter. The ADC was implemented in 0.5-μm 5-V CMOS technology. The chip die area occupies only 4.1 *2.4mm2and dissipates 90mW.

文章基于面积和功耗方面考虑提出了一种低功耗多相变级数非递归梳状滤波器结构,这种滤波器适合高阶过采样sigma delta A/D转换器.抽取滤波器采用Top-down方法设计,用0.6-μm CMOS标准单元实现,相比同样速度下的标准的非递归结构抽取滤波器节省了约1/3面积和功耗.

A 32-bit RISC microprocessor NPUARM is presented in the paper, which is compatible with ARM7TDMI. It is given that the detailed design of the integer execution unit, include ALU,multiplier, barrel shifter and register files. NPUARM core is designed by top-down method. The integer execution unit is described by Verlog HDL. The result of simulation, synthesis, layout and verification shows the design is successful.

针对高性能火箭探空仪探测参数多、数据处理密集、控制复杂、实时性强等特点,提出了主-从处理器体系结构和构造模型链的实时多任务调度方法;采用在系统可编程技术(ISP)实现系统重构和传输数据加密、解密编码.该方法可应用于其它类似飞行器的数据处理.

如何以合理的代价构造尽可能高速的低功耗的乘法器,尤其是位数较宽的乘法器(如32等)是微处理器数据通路设计中极其重要的环节.文中使用一种折衷的补码分段Booth乘法器.经过论证,最后通过布局布线后的结果看出,补码分段Booth乘法器规模小,速度高,非常适合低功耗嵌入式应用.