Design of a highly reliable SPARC-V8 processor for space applications requires consideration singleevent effects including single event upsets, single event transients, single event latch-up, as well as cumulative effects such as the total ionizing dose(TID). In this paper, the fault tolerance of the SPARC-V8 processor to radiation effects is discussed in detail. The SPARC-V8 processor, fabricated in the 65 nm CMOS process, achieves a frequency of 300 MHz with a core area of 9.78 9.78 mm2, and it is demonstrated that its radiation hardened performance is suitable for operating in a space environment through the key elements’ experiments, which show TID resistance to 300 krad(Si), SEL immunity to greater than 92.5 Me V cm2/mg, and an SEU error rate of 2.51 10-4per day.

With the development of RSIC processor architecture ,instruction‐level parallelism has become a research focus .Branch prediction techniques is a key technology to solve control‐related ,and has an important impact on ILP .This paper analyzes the relationship between the superscalar pipeline performance and the factors of branch prediction techniques ,and the deference of the relationship between superscalar pipeline and scalar pipeline ,then gets some analytic functions expressing their relationship based on reasonable assumptions . Finally , this paper forms an in‐depth impact analysis between the branch prediction parameters and the pipeline performance from different perspectives to provide a reference for the study of RSIC processor and branch prediction techniques ,and these parameters include the accuracy of prediction ,the proportion of branch instruction ,the error moment ,the program size ,the pipeline depth and the instruction parallel issue width .

To accurately evaluate the performance of embedded systems,quantitatively analyze the impact of key components in the embedded system on the performance of embedded systems,and give full play to the performance of embedded systems,a method for performance analysis of embedded systems based on the CoreMark benchmark was presented.Firstly,an embedded system for industrial control was established based on the open source Leon2 processor.Then,the characteristics and structure of CoreMark benchmark were analyzed,and the CoreMark benchmark was ported to embedded systems.Finally,the key components of the embedded system which could be configured were analyzed,and the performance speedup of the key components was obtained using comparison strategy.Then the analysis of the macro and micro performance of embedded system could be obtained.

A superscalar pipeline applied Tomasulo's algorithm is presented in this paper. The design begins with a dual-issue superscalar processor based on LEON2. Tomasulo's algorithm is adopted to implement out-of-order execution. Instructions are separated into three different parts and executed by three different function units so as to reduce area and promote execution speed. Results wrote back into registers are still in program order, for the aim of ensure the function veracity. Mechanisms of the reservation station, common data bus, and reorder buffer are presented in detail. The structure can sends and executes three instructions at most at a time. Branch prediction can also be realized by reorder buffer. Performance of the scalar pipeline applied Tomasulo's algorithm is promoted by 41.31% compared to single-issue pipeline.

To accelerateverification speed of scheduling algorithm in heterogeneous architecture and reduce time consumption and verification complexity,this design utilizes software simulation technique to build a multi-task parallel execution model for heterogeneous architecture.This technique uses ERT matrix,communication factor matrix,output array and machine time array to simulate different hardware environment.A parallel model is implemented via serious languagewhich has the function of data forwarding and out-of-order scheduling.No system API is referred considering portability in the designing process.

SpaceWire is a serial,high speed,bi-directional,full duplex,point to point data transfer protocol which is defined by ESA(European Space Agency) in 2003.Its excellent performance in error detection,exception handling,fault protection and fault recovery makes this standard widely used in a variety of space missions such as JWST,LRO,Rosetta,Mars Express and so on.A 8-port high speed SpaceWire routing switch which is proposed in this paper can transfer data smoothly at the rate of 200Mb/s.

Fast growth in information technology extends the means of data transfer. Especially in recent years, many more measures have been proposed in order to raise the data rate. SpaceWire is a serial, high-speed, bi-directional, full duplex, point-to-point data transfer protocol, which is defined by ESA (European Space Agency) in 2003. Wormhole routing adopted by SpaceWire reduces router buffer and makes SpaceWire routers suited to be designed as AISCs. However, blocking problem adhered to wormhole routing limits the network throughput seriously. This paper starts with an introduction to the SpaceWire standard. From the angle of ASIC design, the author deeply analyzes what SpaceWire does to improve router's performance in three aspects. After that, a VLSI design of Spacewire router compliant with the Spacewire standard is presented, and simulation result of this router is provided.

Embedded microprocessors are enormous and complicated systems.Therefore,technology which can make further improvement on the quality of debug work is needed in design and implementation to reduce the time and cost spent on debug work.This thesis is focused on analysis of several common embedded micro processors from the view of debug mode,principle and interface,and makes summarization and comparison.

In order to raise the level of design abstraction and simulation speed of Scalable Processor Architecture(SPARC) processor,a SPARC V8 processor Transaction Level Model(TLM) is designed in this paper.This model is based on TLM2.0 standard and interpretive instruction set simulation technology.Results of the test show that the model can execute and trace SPARC V8 programs exactly and the simulation speed of it is improved two orders of magnitude than Register Transfer Level(RTL) design.

The IBIS (Input/output Buffer Information Specification) is widely adopted in signal integrity (SI) analysis of high speed PCB system. This paper presents a novel approach to improving the accuracy of IBIS simulation by taking a feedback circuit that is usually absent in normal IBIS simulation into consideration. The improved simulation results compared with transistor-level simulation validate the efficiency of the proposed approach.https://pdfs.semanticscholar.org/3f32/310eb7312cf497ee38dcecb588b06283299c.

As the clock rate of digital system increases,the PCB signal integrity(SI)problem becomes unignorable.By taking advantage of IBIS model and analyzing the SI issues on PCB,a necessary SI analysis and simulation method based on the IBIS modeling is presented in this paper.Finally the reflection simulation results of the method on a clock net are introduced as an example.

A Hiberarchy Testbench-Based functional verification method of memory controller in a microprocessor is presented in his paper.This system of verification,which is creating by means of verification methodology manual(VMM)for systemverilog,is reusable and flexible.we creat coverage model by means of classification trees which can close the gap from the specification of a test plan to SystemVerilog testbench generation,so it is very efficient and reduce verification time.The method to verify memory controller in this paper can also be adapted to verify system-on-chip(SoC)system.

This paper presents a coverage-driven constraint random-based functional verification (CCRFV) method of pipeline unit in a microprocessor. The environment of verification, which is created by means of verification methodology manual (VMM) for SystemVerilog, is reusable and can reduce verification time. The model created by combining classification trees, which can ensure to cover complete coverage and to close the gap from the specification of a test plan to SystemVerilog. Using this environment of verification, we can not only know whether there are bugs in the design under test (DUT) or not, but also can easily locate design errors.

In this work,three logical fault tolerant techniques are applied on a SpaceWire interface circuit after analysis of SpaceWire error handling mechanism,as the reliability is of great importance to this communication standard which is specially presented for spacecraft onboard communication.The techniques are including:1.An implementation of SED-DED Hamming encoding on module FIFO,2.Fault tolerant design of state machine,3.The implementation of TMR registers.Those techniques are all implemented on Xilinx FPGA with evaluation and analysis of penalty of performance and area.

A novel low-voltage low-power LVDS driver, which can operate under the 1.8V supply voltage, is proposed. By adding pre-emphasis, merging the switch current sources, and making the switch current sources work in subthreshold region, data rate of this driver attains to 1.5 gigabits-per-second and power consumption falls by 60% to 9.78 mW. The good characteristics make this LVDS driver feasible to be used in the low voltage and low power applications.

This paper describes the architecture and implement of the specific processor,SPARC_-V8FTS,designed for fault tolerant system.The SPARC_-V8FTS integrates duplicate core processor and the Fault-tolerant manager.The core processor is 32-bit micro processor based on the SPARC V8 specification.The Fault-tolerant manager provides the mechanism of error detection,error diagnosis,error recovery from a transient fault,and reconfiguration that makes the SPARC_-V8FTS to a single processor system to run continuously when a permanent fault takes place.SPARC_-V8FTS drastically reduces the hardware count of a system,and performs all the fault tolerant operations.It provides high system reliability with low performance overhead.

The Elmore delay RC metric,used widely to analysis FPGA interconnect delay,becomes ineffective for deep submicron technologies.Many interconnect delay models have been proposed by analyzing the moments of the impulse response, either computationally expensive or less accurate.A new delay metric is presented for FPGA based on the first three moments of the impulse response,which has simple closed form expression and fast computation speed.The new metric is theoretically proven to be strictly less than the Elmore metric and is a provably stable approximation.The average error is less than 1% for far ends.In the test for commercial FPGA,the average error shrinks more than sixty percent to the Elmore delay.

This paper describes the architecture and implementation of the application specific processor, the NBHAWK, which designed for fault-tolerance. The processor tolerates transient SEU errors. We propose a novel approach: Optimal Odd-weight-column Codes ,to check the transient fault of register-file, which can reduce the penalty of recovering the pipeline. In addition, a lot of efficient techniques are used to improve the reliability of the processor ,such as TMR registers, TMR clock, on-chip EDAC, parity, and forced cache miss. The chip was manufactured on the smic 0.18μm CMOS technology. The radiation-injection tests showed that all of the injected errors (＞ 50,000) were corrected or handled successfully. The 252CF radiation-source, 3.5 u Ci radiation-activity, and 43 MeV.cm2/mg.average LET were used to error-injection.