This paper presents a novel front-end Application Specific Integrated Circuit (ASIC) dedicated to CZT detectors for positron-emission tomography (PET) imaging applications. The ASIC consists of a preamplifier using split-leg topology, a variable gain amplifier, a time-interleaved ramp ADC and a timing controller. The design techniques of these circuit blocks are discussed in detail. Meanwhile, the digital CR-RC shaping and the digital trapezoidal shaping are introduced as well. A prototype ASIC is implemented in CMOS 0.35 μm process. The preliminary results have been obtained. The detection range of the gamma ray is from 11.2 keV to 550 keV. The non-linearity of the output voltage is less than 3%. The gain of the readout channel is 40.2 V/pC. The test results show that the proposed front-end electronics is appropriable for PET imaging applications.

This paper presents a novel a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascode amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm × 2.1 mm. The input range of the ASIC is from 2000 e- to 100000 e-, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications.

This paper presents a novel front-end electronic system dedicated to CZT detectors for positron-emission tomography (PET) imaging applications. It is implemented by full-customized readout application-specific integrated circuits with a post digital pulse shaping algorithm in FPGA. In the front-end readout ASIC, a preamplifier, a variable gain amplifier, a multiple-point sampling ramp ADC are integrated together. The digital CR-RC shaping and the digital trapezoidal shaping are implemented in a FPGA. A prototype front-end electronic board is implemented. Experiments results have been obtained. The detection range of the gamma ray is from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The test results show that the proposed front-end electronics is appropriable for PET imaging applications.

Pico-satellite,which features low cost and flexiblity,is a hot topic in aerospace applications. Due to the limitation of size and weight,design of On-Board Computer( OBC) for pico-satellite systems is different with that in the larger satellites. This paper introduces the modular design techniques of an OBC based on Commercial Off-the-Shelf ( COTS) devices for pico-satellites. The chip selection is important for electronic system design. The selection of the suitable COTS devices is performed by using Technique for Order of Preference by Similarity to Ideal Solution( TOPSIS) method. Two versions of prototype OBC systems based on different types of low power MCUs which are selected by TOPSIS method are implemented. The running speed, power consumption, and operational temperature of two OBC systems are tested and compared. When operational temperature is 27℃ and main frequency is 8 MHz,the MIPS of OBC system based on MSP430 and ATxmega are 7. 449 and 6. 781,respectively. The running times of addition are 0. 613 μs and 1. 381 μs,respectively. The power consumptions of addition are 38. 224 mW and 54. 411 mW, respectively. The performance of the OBC system based on MSP430 is better. Two OBC systems can work correctly at -40℃ to 85℃.

CMOS Active pixel sensors (CMOS APS) are attractive for use in the innermost layers of charged particle trackers, due to their good tradeoffs among the key performances. However, CMOS APS can be greatly influenced by random telegraph signal (RTS) noise, which can cause particle tracking or energy calculation failures. In-depth research of pixels' RTS behavior stimulates the interest of the methods for RTS noise detection, reconstruction and parameters extraction. In this paper, a real-time auto-detection method is proposed, using real-time Gaussian noise standard deviation as the detection threshold. Experimental results show that, compared with current methods using signal standard deviation as the thresholds, the proposed method is more sensitive in multi-level RTS detection and more effective in the case of RTS noise degradation.

In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45keV to 281keV. The gain is larger than 100mV/fC. The equivalent noise charge (ENC) of the ASIC is 53e− at zero farad plus 10e− per picofarad. The power dissipation is less than 4.4mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200krad (Si).

In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascode amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuits is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above topology, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm × 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per picofarad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 3 mW/channel.

CMOS pixel sensors (CPS) are attractive for use in the innermost particle detectors for charged particle tracking due to their good trade-off between spatial resolution, material budget, radiation hardness, and readout speed. With the requirements of high readout speed and high radiation hardness to total ionizing dose (TID) for particle tracking, fast readout CPS are composed by integrating a data compression block and two SRAM IP cores. However, the radiation hardness of the SRAM IP cores is not as high as that of the other parts in CPS, and thus the radiation hardness of the whole CPS chip is lowered. Especially, when CPS are migrated into 0.18-m m processes, the single event upset (SEU) effects should be also considered besides TID and single event latchup (SEL) effects. This paper presents a radiation-hardened SRAM with enhanced radiation hardness to SEU. An error detection and correction (EDAC) algorithm and a bit-interleaving storage strategy are adopted in the design. The prototype design has been fabricated in a 0.18-m m process. The area of the new SRAM is increased 1.6 times as compared with a non-radiation-hardened SRAM due to the integration of EDAC algorithm and the adoption of radiation hardened layout. The access time is increased from 5 ns to 8 ns due to the integration of EDAC algorithm. The test results indicate that the design satisfy requirements of CPS for charged particle tracking.

In order to protect the security of valuables,an anti-theft system based on ultra-low power MSP430 and Blue-tooth technology was designed. The burglar alarm is controlled by application software developed for Android smartphone. It’s easy to operate. Smartphone users are the potential users of burglar alarm. The smartphone APP can judge the distance between the cellphone and burglar alarm by reading the RSSI values of the burglar alarm Bluetooth. The results obtained in a lot of experi-ments show that the burglar alarm can realize the functions of initiative alarm and anti-theft. The software’s measuring accuracy is 1 m in the range of 5 m. The design scheme has better practicability.

Based on network calculus,a technique was proposed for analyzing communication delay bounds for individual flows in Networks on Chip(NoC)using Improved Asymmetric Multi-channel Structure(IAMCS)of router.The flow control blocking,switch blocking and channel blocking of IAMCS router were analyzed. Then,corresponding equivalent service models of them were constructed.By extending the router service model to the analysis of the entire network,the forward equivalent service analysis network was established.Furthermore,using the contention tree model, the equivalent service curves were computed for individual flows in the equivalent service analysis network,and then their delay bounds were derived.Experimental results show that the delay bound model can restrict the maximum delay of simulation,and the bounds is compact.

In order to solving the problem of weak observability and low positioning precise in bearing-only target tracking,this paper improves a method that employing radar to support electro-optical system with batch ranging for object localization,which succesfully improves not only the observability of target tracking,but also the object positioning precision.The technology could greatly reduce the risk of exposure of radar,and makes full use of electro-optical system and radar.Finally,it increases the total combat effectiveness greatly.

Based on the multi-channel front-end readout circuit and high-speed high-resolution ADC of high performance PET front-end electron micro system structure,a 12 bit 10 MHz pipeline ADC is designed.The whole circuit consist of S/H circuit,MDAC circuit,Sub_ADC circuit,delay alignment circuit,digital correction circuit,two-phase non-overlap clock circuit.The whole circuit is designed in TSMC 0.18 μm mixed signal CMOS technology.Simulation results show that,pipeline ADC has-0.6832/0.5994LSB DNL,-0.7997/0.7576LSB INL,62.1406 dB SNR,and 10.03 bit ENOB.The pipeline ADC presented in this paper satisfy the design requirements of the system.

A high-speed and high-resolution CMOS comparator for Wilkinson A/D converter was designed.The comparator was comprised of three preamplifiers and one output stage realized by a current operational amplifier.An open-loop architecture was adopted for the comparator,and multiple stages were cascaded to achieve the desired gain and speed.Output offset storage was adopted to cancel offset voltage of the amplifier.The circuit was designed based on 3.3-V TSMC 0.18 μm CMOS process.Results from Spectre simulation showed that the proposed comparator had a resolution of 0.4 mV at a maximum sampling frequency of 1 MHz,and a propagation delay less than 20 ns,which satisfied the requirements of 12-bit Wilkinson A/D convertor.

针对机载红外图像中运动弱小点目标检测的难题,提出了一种基于PSO-GA训练参数的形态学滤波器。以粒子群优化算法（Particle Swarm Optimization,PSO）为主线,按PSO算法中标准的速度和位置更新,遗传算法（Ge-netic Algorithm,GA）采用新的区间离散化编码和自适应的主次式交叉与变异算子,将遗传算法与粒子群优化算法的自动更新特征结合在一起,通过优化搜索全局空间获得形态学滤波器的最优参数,进而确保优化的形态学滤波器具有良好的滤波性及时效性。通过对低信噪比红外图像（SNR约为2）的测试,检测概率可以达到98%以上,与利用神经网络（Neural Network,NN）训练结构元素后的Top-Hat形态学滤波器相比提高了2%～3%。与GA算法相对,训练算法效能提高20%,提高了搜索最佳值的能力。

In space radiation and nuclear radiation environments,total ionizing dose(TID) effects have serious impact on reliability and lifetime of SRAM's fabricated with commercial CMOS process.Four types of TID tolerable memory cells were designed for SRAM,and their radiation tolerance to single event latchup,single event upset and TID effects was analyzed,as well as their speed and area.It has been shown that these cells,which had excellent TID tolerance and reasonable SEE tolerance,could be used for high-level radiation tolerant SRAM's using commercial CMOS process.

This paper presents a low-noise front-end readout application specific integrated circuit (ASIC) for CZT detectors. A cascode amplifier based on split-let topology is selected to realize the charge-sensitive amplifier (CSA) to achieve low noise performances. A leakage-current-compensation circuit is added to suppress the leakage current of from 0 to 10 nA. The output of the CSA is connected to a slow shaper implemented by a CR-(RC)2 semi-Gaussian architecture. In the time branch, the CSA output is followed by a fast shaper for the trigger acquisition. A digital monostable circuits is designed to adjust the delay of trigger signals so that the peak value of the shaped voltages can be tracked. The sampled voltages are stored into an analog memory. Based on the above topology, a 16-channel front-end readout prototype chip (named as SENSROC5) is designed and implemented in 0.35 μm CMOS process. In this chip, the radiation-hardness layout techniques are adopted. The die size is 2.12 mm×4.60 mm. The input range of the ASIC is from 2000 e-to 180000 e-, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 1 MeV. The post-simulated results are listed in the following. The gain of the readout channel is 40.2 V/pC. The ENC is 90 e- at zero farad plus 15 e- per picofarad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 16.5mWplus 3.1 mW/channel.

This study presents hardware architectures performing correctly rounded Floating-Point (FP) multioperand addition and dot-product computation, both of which are widely used in various fields, such as scientific computing, digital signal processing, and 3D graphic applications. A novel realignment method is proposed to solve the catastrophic cancellation and multi-sticky bits. Only one rounding operation is performed in both of the proposed FP multi-operand adder and dot-product computation unit. Implementation results show that our architectures not only can produce correctly rounded results, whose errors are less than 0.5 ULP (Unit in the Last Place), but also have reduced delay comparing with the traditional network architecture, which uses 2-operand FP adders and multipliers to perform multi-operand addition and dot-product computation.

The crosstalk between CMOS pixel sensors (CPS) degrades the performances of detector systems. Moreover, power distribution becomes a challenge in the future detectors for high energy physics experiments. In order to address these problems, a power management is proposed. Power supply voltages and reference voltages are internally generated in CPS. Two full on-chip linear regulators are proposed in this paper. Low area, low power consumption and low noise are achieved by a novel structure. The regulators have been designed and fabricated in a 0.35-μm commercial process. The measurement results are also presented.

A network security evaluation model based on Finite State Automata(FSA)is proposed.According to all kinds of security information and its related properties in the model,the states are used to indicate the security situation of both attack side and defense side;the state transitions are used to indicate the dynamic security situation of the action for both attack side and defense side;the transition diagram is used to describe the transition processes of security status.Experimental results show that the model is more suitable for Network security modeling with simulating the intrusion processes of attackers and the security defense process.

The utilization wall, which lead to the Dark Silicon phenomenon, indicates that the energy efficiency will be the primary constraint in micro-processor architecture design in the near future. Since the stream processing natively has the high energy efficiency feature, we proposed the many-core Longtium stream processor (SP) architecture, which includes a coarsegrained reconfigurable array (CGRA), a simplified star-mesh static NoC and software managed stream memory system. In this paper, we demonstrate the evaluation methodology for Longtium SP. The methodology includes the FPGA prototyping system, baseline processor, software tool-chains, golden model and benchmarks. The FPGA prototyping system show that Longtium SP could averagely speedup the program by 11.6X and improve the energy efficiency by 177X, after taking the chip area into account it still could speedup the program by 5.8X compared to the dual-issue baseline RISC processor.