This work investigates the coupling effect between total ionizing dose (TID) radiation and hot carrier injection (HCI) in 28 nm bulk nMOSFETs, with systematic variation of stress sequence under accelerated HCI stresses at $\mathbf{1} \text{Mrad}\left(\text{SiO}_{2}\right)$ total dose. Experimental results reveal strong stress-sequence dependence: under 1.8 V HCI stress, the SPR (Stress Post Radiation) sequence exhibits a threshold voltage shift ($\Delta \mathrm{V}_{\text {th }}$) that is significantly larger than those under RPS (Radiation Post Stress) and RWS (Radiation With Stress). At lower stress voltages, $\Delta \mathbf{V}_{\text {th }}$ remains minimal with negligible transconductance degradation. Subthreshold swing (SS) analysis confirms that stress sequence modulates interface trap generation efficiency, with SPR showing strongest degradation due to STI chargeenhanced lateral electric fields. These findings demonstrate that stress history fundamentally alters degradation pathways in 28 nm bulk devices-a critical factor currently missing in reliability models for space electronics.

This work presents a 0.03-to-40GHz reconfigurable CMOS receiver (RX) for millimeter-wave (mm-wave) software-defined radios (SDRs). To achieve continuous ultra-wideband operation while interfacing to a single-ended $50~\Omega $ antenna port, the RX employs a dual-channel hetero-frequency combining architecture with embedded switching, enabling independent optimization of a 0.03-to-20GHz low-frequency (LF) path and a 15-to-40GHz high-frequency (HF) path. The high-frequency path employs an inductive-mutual cascode LNA with transformer-based bandwidth extension, while the low-frequency path uses an LNA with an active balun load. An extremely wide-band local oscillator (LO) generation circuit with a hierarchical buffer scheme is introduced for generating quadrature signals. Measurements demonstrate continuous 0.03-to-40GHz frequency coverage with NF below 5dB, and a conversion gain exceeding 20dB with 4dB step control up to 44dB. The measured in-band IIP3 of the RX is above −10dBm from 0.1-to-7GHz and above −20dBm from 7-to-40GHz. The RX supports modulation up to 1024-QAM and achieves a maximum measured data rate of 7.2Gb/s with 64-QAM.

With the rapid advancement of information technology, the demand for high-reliability and energy-efficient data processing and storage systems has grown significantly. Emerging memory technologies offer promising solutions due to their high access speeds, low power consumption, nanoscale dimensions, and CMOS compatibility. Non-volatile SRAM (NVSRAM) has attracted attention for combining SRAM with emerging memory technologies, enabling nanosecond-scale data backup and recovery with energy consumption reduced to the picojoule-per-bit level. This review identifies key reliability challenges associated with NVSRAM based on emerging memory devices, with a focus on cell design and optimization strategies, system-level architectures and control schemes, and extended applications in computing-in-memory. Moreover, reliability challenges at the device, system, and extreme-environment levels are discussed. This work aims to provide a theoretical and technological foundation for future high-reliability, energy-efficient memory solutions, while highlighting open challenges and the envisioned development of dedicated simulation frameworks for NVSRAM design and evaluation.

This paper proposes a novel SiC trench MOSFET (TMOS) that embeds a poly-Si PIN diode (PS-PIN) within the gate groove. By forming the P+ anode, N-, and N+ cathode regions from bottom to top through multiple polysilicon depositions, an architecture with anti-parallel PS-PIN between the gate and source terminals is achieved (PS-PIN-TMOS), where the P+ anode is short-circuited to the source and the N+ cathode is connected to the gate. When a short-circuit (SC) event occurs in the SiC PS-PIN-TMOS, its lattice temperature rises with the increase in drain current. Leveraging the temperature-dependent reverse leakage characteristic of the PS-PIN, the current in the drive circuit begins to increase, thereby dynamically regulating the voltage distribution across each component of the driving loop. This sequential adjustment results in a reduction of the gate voltage, ensuring safe turn-off of the SiC PS-PIN-TMOS ultimately. TCAD simulation results confirm that the SiC PS-PIN-TMOS is completely immune to the SC failure. Furthermore, compared to the traditional SiC trench MOSFET (C-TMOS), the proposed structure exhibits lower reverse transfer capacitance C-RSS , gate charge Q(G) , gate-to-drain charge Q(GD) , and total power loss P-t , demonstrating higher potential for high-frequency applications.

In this study, heavy-ion irradiation tests were used to evaluate the soft-error tolerance of the conventional stacked structures and higher radiation hardness structures in the attempt to reduce the SEU sensitivity. Test data show that flip-flop (FF) using the traditional stacked structure approach exhibit only a 19% smaller single-event upset cross section compared to unhardened FF. The conventional stacked-FF are weaker against soft errors in a fully-depleted silicon on insulator (FDSOI) process. Technology computer-aided design (TCAD) simulations are used to illustrate the effect of additional charge collection. This effect is due to the process-dependent CnRX structure with a virtual transistor at the node protected by the stacked structure. The simulations show that this effect reduces the hardening efficiency. An insertion structure is designed to decouple connection relationship. Under heavy-ion irradiation with an LET of 75.4 MeV-cm²/mg at normal incidence and a 60° tilt angle, the novel stacked-FF with decoupling structures showed no errors. Experimental results demonstrate that the proposed FF is much stronger against soft errors than the conventional stacked FF, also achieving collaborative hardening design against angular incidence without incurring additional overhead.

Hardware-based security primitives have become critical to enhancing information security in the Internet of Things (IoT) era. Physical unclonable functions (PUFs) utilize the inherent variations in the manufacturing process to generate cryptographic keys unique to a device. Reconfigurable PUFs can update cryptographic keys for enhanced security in dynamic operational scenarios involving huge amounts of data, which makes them suitable for implementation in CMOS-integrated spin-orbit torque magnetic random access memory (SOT-MRAM) chips. However, a key challenge is achieving real-time reconfiguration independent of the environmental conditions, particularly the operating temperature. We propose a dual-pulse reconfiguration strategy for PUF design in CMOS-integrated SOT-MRAM chips that effectively widens the operating window and achieves resilience across a wide range of operating temperatures without the need for dynamic feedback that overly complicates circuit design. The proposed strategy lays a solid foundation for the next generation of hardware-based security primitives to protect IoT architectures.

This article presents a 2-element 18-50-GHz multiband phased-array transceiver supporting 5G frequency range 2 (FR2) bands (n257/n258/n259/n260/n261/n262) and FR2 nonterrestrial network (NTN) bands (n510/n511/n512). The design incorporates a frequency-reconfigurable power amplifier (PA) utilizing an asymmetric coupled multimode transformer and a triple-coupled frequency-reconfigurable network (TC-FRN), enabling band-shifting, bandwidth expansion, and spectrum reconstruction across 18-30 and 30-50 GHz. A tunable image-rejection filter (TIRF) is integrated into the TX path to enhance image-rejection capability and energy efficiency. In the receive path, a dual-path multiband low-noise amplifier (LNA) minimizes noise figure (NF) and power consumption while extending bandwidth. The phased-array transceiver employs a local oscillator (LO) phase-shifting architecture, incorporating a proposed distributed LO chain and an ultrawideband bidirectional mixer to reduce complexity and power consumption. The proposed transceiver is fabricated in a standard 65-nm bulk CMOS process. With the concerted efforts of all components, the transceiver can support complex modulated signals up to 64 QAM with a 400-Msys/s symbol rate from 18 to 50 GHz and maintain adjacent channel leakage ratio (ACLR) better than -30 dBc. The full path link performance is validated with 400-MHz 64-QAM signals and achieves error vector magnitude (EVM) results better than -25dB. The measured peak OP1dB is 16.7 dBm with 27.3-dB S21 at 28 GHz in the TX mode, and the minimum NF is 7.1dB with 35-dB S21 and -35.3-dBm IP1dB at 22 GHz in the RX mode. Benefiting from the TIRF and frequency-reconfigurable PA-LNA, an image-rejection ratio (IMRR) of 28.2-to-64.7 dBc can be achieved for the full path (TX-to-RX). Each element front end (FE) consumes DC power of 244 mW from 1 to 2 V in the TX and 53 mW in the RX, and the corresponding chip total power consumption is 434 and 337 mW.

The optimized sidewall interface quality (OSIQ) strategy leverages the polarized electric field induced by forward-voltage stress (FVS) in a ferroelectric dielectric (FD) to dramatically relieve the interface state density at trench sidewalls. This enables efficient exploitation of the higher thermal conductivity along the [100]-oriented trench sidewall for beta -Ga2O3 trench devices, thereby establishing a practical electrothermal co-design pathway that effectively mitigates the intrinsic low thermal conductivity limitation of beta -Ga2O3. This work further systematically investigates the reverse I - V characteristics of beta -Ga2O3 MOS-Type trench diodes with ferroelectric HfCeO2 dielectric, revealing that FVS concurrently degrades the dielectric properties of HfCeO2 and increases the border trap density. These synergistic degradation mechanisms substantially impair the device's reverse I - V performance. The findings offer critical theoretical insights and guidance for advancing robust electrothermal co-design in beta -Ga2O3 trench devices via the FD-OSIQ methodology.

Spin-orbit torque (SOT) magnetic tunnel junctions employ decoupled read/write paths, offering the advantage of high endurance. Designing multiple pillars with a shared SOT track enables further area savings in SOT devices. In such quasi-two-terminal SOT devices, a vertical-voltage-based selective operation is employed as an alternative to CMOS gating. However, high-volume experimental data on the selectivity of quasi-two-terminal SOT devices remain limited, as selectivity cannot be predicted owing to the complexity arising from nonideal factors. This study evaluates selectivity through extensive experimental testing, with detailed rate curves also provided. To the best of our knowledge, this is the first report describing the degradation of selectivity caused by the ballooning effect. To enhance selectivity, double-pulse writing is proposed and demonstrated, resulting in improved write error rate curves. The findings of this study are crucial for the practical implementation of quasi-two-terminal SOT devices in memory applications and provide experimental guidance for application layers such as circuit design.

Artificial intelligence (AI) is propelling space exploration into a new era. Synergistic breakthroughs in chip design and high-speed communications have facilitated the large-scale deployment of on-board satellite computing. Assessing the reliability of these systems via fault injection (FI) remains difficult due to the massive computational demands of Convolutional Neural Networks (CNNs) and the complex architectures of Neural Processing Units (NPUs). This research presents a high-precision, efficient FI methodology specifically tailored for NPU architectures to optimize both evaluation accuracy and execution efficiency. Implementing a hierarchical injection strategy to identify fault-sensitive layers minimizes computational overhead while ensuring statistical validity. Experimental results on the ResNet-50 network demonstrate that the proposed methodology constrains accuracy degradation to less than 0.1% while achieving a 60.80% reduction in total execution time.

Spaceborne neural processing units (NPUs) increasingly support real-time deep-learning inference, but their dense multiply-accumulate arrays are vulnerable to radiation-induced soft errors. Conventional radiation-hardening methods improve reliability through hardware redundancy, but they incur substantial area, performance and compiler-mapping overheads. This paper proposes tile-resilient algorithm-based fault tolerance (TR-ABFT), a software-scheduled, detection-oriented scheme for quantized NPU inference. TR-ABFT generates checksum information at tile granularity and maps checking tasks onto the original processing element (PE) array without changing the hardware topology. To make ABFT compatible with INT8 datapaths, we design two checksum-coding strategies: checksum decomposition and modulo-239 checksum coding. The modulo-239 scheme removes structural missed detections for two-bit flips with bit-position spacings in (1, 31), while preserving compatibility with signed INT8 inputs. Evaluations on ResNet, YOLOv8, and RT-DETR show that, on a 16 & times;16 array, TR-ABFT introduces only 6.37% to 24.61% additional computational overhead. By converting spatial redundancy into schedulable temporal redundancy, TR-ABFT preserves systolic-array regularity and provides a low-overhead reliability-enhancement mechanism for space-grade neural-network accelerators.

As emerging nonvolatile units, devices based on spin-orbit torque (SOT) demonstrate CMOS compatibility and high reliability, particularly those used in-plane magnetic anisotropy magnetic tunnel junctions (IMA-MTJs). Pulse shaping offers new opportunities for low-energy writing. However, pulse-shaping optimization for enhancing the writing performance of IMA-SOT-MTJs remains unexplored. This study systematically investigated the magnetization switching behavior and dynamic characteristics of an IMA-SOT-MTJ by injecting triangular pulses. Experimental results confirmed that triangular-pulse writing exhibited higher energy efficiency than square-pulse writing. Macrospin simulations qualitatively agreed with the experimental findings under an induced thermal fluctuation. The results indicated that the peak of the triangular pulse should not occur in the early phase of the pulse cycle. Overall, our findings provide valuable experimental evidence for circuit design and practical applications, contributing to the development of energy-efficient writing strategies.

This work presents a radiation-hardened 28 nm SRAM with Design-Layout Co-Optimized 14T cell (DLCO-14T) and double mode redundant peripheral circuit for space applications. The proposed architecture exhibits strong resilience to single-event effects (SEE), withstanding laser irradiation at a linear energy transfer (LET) of up to 60 MeV $\cdot $ cm2/mg. The memory cell achieves a normalized critical path distance (NCPD) of 67%, approximately twice that of conventional rad-hard designs. By integrating a dual-mode decoding strategy, dual-port cell configuration, and a DICE-latched sense amplifier (DL-SA), the SRAM remains functional at operating frequencies above 500 MHz under radiation. A mixed-mode redundancy (MMR) delay chain in the sense amplifier control circuitry achieves single-event transient (SET) immunity with an area overhead of 140%. Experiment results confirm no failure at laser injecting at hardened zone and an 87.9% soft error rate reduction at laser injecting at non-hardened zone, demonstrating high reliability for space systems.

Total Ionizing Dose (TID) effects and aging mechanisms such as Bias Temperature Instability (BTI) are critical factors constraining the reliability of integrated circuits operating in radiation environments. Traditional simulation methods typically treat TID and aging effects in isolation and rely on multi-corner process libraries, resulting in cumbersome workflows, an inability to simulate coupled multi-stress accumulation processes, and poor model portability. This paper proposes a standardized multi-stress simulation framework built upon the Open Model Interface (OMI). Leveraging the standard C-language API provided by OMI, the TID degradation mechanism based on physical trap density models and aging models are encapsulated into independent dynamic libraries, achieving seamless integration with commercial SPICE simulators. Referencing compact model theories for MOSFETs and radiation-aging coupling effect models, an OMI model supporting dynamic configuration of dose rate, cumulative dose, and time stress is constructed. Through case studies of ring oscillators, the effectiveness of the framework under single TID stress and coupled TID-aging stress was validated. Experimental results indicate that compared to traditional multi-library methods, this framework significantly reduces process library management complexity and successfully achieves continuous simulation of circuit performance as a function of both dose and time. This method provides an efficient, portable, and multi-physics coupled standardized tool flow for radiation-hardened integrated circuit design.

This article presents a comparative study on the performance degradation of quasi-vertical GaN Schottky barrier diodes (SBDs) with different drift-layer thicknesses (Sample A: 1 & micro;m N--GaN; Sample B: 4.5 & micro;m N--GaN) under 200 keV proton irradiation. Both devices exhibit a slight reduction in Schottky barrier height after irradiation, which is attributed to radiation-induced acceptor-like interface states participating in charge transport. At the same applied bias, Sample B shows a more pronounced degradation in electrical performance due to the spatial coupling between the irradiation-induced defect distribution and the high electric field region. In Sample B, the coincidence of the defect peak with the high-field region in the drift layer enhances trap-assisted tunneling (TAT) and electric-field variation. In contrast, Sample A benefits from a structural design in which the defect peak is spatially separated from the critical depletion region, thereby mitigating degradation. Furthermore, the competing roles of donor-and acceptor-like defects in modulating the depletion width and conduction-band bending are identified as a fundamental mechanism governing the reverse leakage behavior.

Spin-orbit torque magnetic random-access memory (SOT-MRAM) is a promising nonvolatile memory technology, offering low power consumption and high-speed read/write performance. The inherent fabrication variations within SOT units generate static entropy, making them suitable as carriers of physically unclonable functions (PUFs). Integrating PUFs with SOT-MRAM chips enhances hardware security and improves the fabrication feasibility, area efficiency, and cost-effectiveness. In this work, we present a highly reliable SOT-MRAM-based PUF design, where the introduction of one-time programmable significantly enhances PUF reliability, such as a 44 & times; improvement in read margin, an optimal inter/intra-Hamming distance ratio, and zero bit error rate. Furthermore, the proposed OTP-PUF exhibits exceptional resilience to external magnetic fields (up to 500 Oe) and stable readout across an extended temperature range (-55 degrees C-150 degrees C), guaranteeing reliability in harsh environments. The results demonstrate that SOT-MRAM-based OTP-PUF presents a promising solution for secure memory systems.

This work presents a 0.03-to-40 GHz reconfigurable CMOS receiver (RX) for millimeter-wave (mm-wave) software-defined radios (SDRs). To achieve continuous ultra-wideband operation while interfacing to a single-ended 50 Omega antenna port, the RX employs a dual-channel hetero-frequency combining architecture with embedded switching, enabling independent optimization of a 0.03-to-20 GHz low-frequency (LF) path and a 15-to-40 GHz high-frequency (HF) path. The high-frequency path employs an inductive-mutual cascode LNA with transformer-based bandwidth extension, while the low-frequency path uses an LNA with an active balun load. An extremely wide-band local oscillator (LO) generation circuit with a hierarchical bu ffer scheme is introduced for generating quadrature signals. Measurements demonstrate continuous 0.03-to-40 GHz frequency coverage with NF below 5 dB, and a conversion gain exceeding 20 dB with 4 dB step control up to 44 dB. The measured in-band IIP3 of the RX is above -10 dBm from 0.1-to-7 GHz and above -20 dBm from 7-to-40 GHz. The RX supports modulation up to 1024-QAM and achieves a maximum measured data rate of 7.2 Gb/s with 64-QAM.

Spin-orbit torque (SOT)-based multi-level cell (MLC) shows the advantage of area saving by sharing the write path and reducing the number of transistors. However, to our knowledge, it is challenging to accurately write different states into SOT-MLC due to intrinsic bottlenecks such as inter-cell interference and ballooning-like effect. In this work, we firstly propose and experimentally realize structural optimization of SOT-MLC using the shared top electrode and varying-width heavy metal layer. Furthermore, we improve the writing method by utilizing the double-pulse scheme to experimentally reshape multiple switching probability curves. Meanwhile, the mutual interaction between the adjacent cells is modeled and analyzed. Our work enables the SOT-MLC to be applied in both accurate storage and fault-tolerant computing scenarios.