Radio frequency (RF) and analog/mixed-signal (AMS) integrated circuits (ICs) are key enabling components for mobile and wireless communications and their advancements continue to drive the growth of the related semiconductor market. The circuit and technology requirements for RF and AMS ICs in mobile and wireless communications are quite different in comparison to that for digital logic and memory applications. Many tradeoffs and unique considerations have to be applied for RF and analog/mixed-signal technology development and circuit implementations. This paper reviews the critical circuit and technology requirements for RF and analog/mixed-signal ICs for mobile and wireless communications and highlights future challenges and opportunities

The International Technology Roadmap for Semiconductor (ITRS) Radio Frequency and Analog/Mixed-Signal (RF and AMS) Wireless Technology Working Group (TWG) addresses device technologies for wireless communications covering both silicon and III-V compound semiconductors. This paper discussed the roadmap and the figures of merit (FoM) used to characterize both active and passive devices critical for typical radio front end designs. The trends, challenges and potential solutions was reviewed and address the intersection of silicon and III-V compound semiconductors

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f(T), maximum frequency of oscillation f(MAX) at unit power gain, noise, breakdown voltage,.capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices.

An ultralow-standby-power technology has been developed in both 0.18-mum and 0.13-mum lithography nodes for embedded and standalone SRAM applications. The ultralow-leakage six-transistor (6T) SRAM cell sizes are 4.81 mum(2) and 2.34 mum(2) corresponding respectively to the 0.18-mum and 0.13-mum design dimensions. The measured array standby leakage is equal to an average cell leakage current of less than 50 fA per cell at 1.5 V, 25degreesC and is less than 400 fA per cell at 1.5 V, 85degreesC. Dual gate oxides of 2.9 nm and 5.2 nm provide optimized cell leakage, I/O compatibility, and performance. Analyses of the critical parasitic leakage components and paths within the 6T SRAM cell are reviewed in this paper. In addition to the well-known gate-oxide leakage limitation for ULP technologies, three additional limits facing future scaled ULP technologies are discussed.

The FIELDAY program simulates semiconductor devices of arbitrary shape in one, two, or three dimensions operating under transient or steady-state conditions. A wide variety of physical effects, important in bipolar and field-effect transistors, can be modeled. The finite-element method transforms the continuum description of mobile carrier transport in a semiconductor device to a simulation model at a discrete number of points. Coupled and decoupled algorithms offer two methods of linearizing the differential equations. Direct techniques are used to solve the resulting matrix equations. Pre- and post-processors enable users to rapidly generate new models and analyze results. Specific examples illustrate the flexibility and accuracy of FIELDAY.

This paper reports up to 100/spl times/ improvement in hot-electron lifetime in high-performance CMOS, without impacting process cycle time or thermal budget. This was achieved by combining deuterated-film processing with standard pre-metal and post-metal anneals in deuterated forming gas. CMOS transistors, fabricated in a single and dual-oxide process, were studied. The effects of additional back-end-of-line processing on multilevel metal processes were evaluated. We also demonstrate for the first time the effect of incorporating deuterated processing on CMOS devices integrated with copper interconnects where lower temperature/time post-metal anneals are expected.

The effects of velocity saturation on the unity gain-bandwidth product f/sub t/ and transconductance g/sub m/ of n-p-n and p-n-p heterojunction bipolar transistors (HBTs) with Ge/sub x/Si/sub 1-x/ bases are described and simulated. For the n-p-n device, velocity saturation combined with a valence-band offset at the base-collector junction causes accelerated g/sub m/ and f/sub t/ rolloff for current densities greater than the knee current for the Kirk effect. For the p-n-p device, the g/sub m/ and f/sub t/ are degraded for all current densities. These limitations combine with the limits imposed by dislocation formation due to strain in the pseudomorphic layer to impose constraints on the design of Si/Ge/sub x/Si/sub 1-x//Si HBTs.<>

An overview is presented on the types of problems encountered in semiconductor technology development that are actively studied today via simulation methods. Most of the simulation examples presented here are ones that have been explicitly used in actual industrial semiconductor device design cycles to aid in the optimization of device structures. The examples described here include process simulations, such as the diffusion of dopant atoms, oxidation, etching, deposition, and epitaxial growth, as well as device simulations, which predict the flow of charge carriers and field distribution within a semiconductor device, given its material structure and operating conditions. The main aim here is to illustrate, by example, some of the capabilities of state-of-the-art simulators used in characterizing and predicting semiconductor process and device-related phenomena. We will attempt to outline the degree of sophistication of the physics incorporated in such simulation programs, and provide some contrast to the fundamental physics required for a complete physical description. As will be indicated, simulation development necessarily involves molding the appropriate physical models and numerical algorithms into a package that can be handled in a reasonable length of time by modern computing systems. We briefly outline some of the advances that have been made, and some concerns that remain, in such simulation development.

The combination of velocity saturation, and a valence band offset at the base-collector junction reduces the performance of double heterojunction bipolar transistors at high injection levels because of the formation of a retarding potential barrier. This barrier causes saturation of the transconductance, early onset of high level injection in the base, and a rapid decrease of fT for J C>JK. An analytical model is developed for computation of the barrier height and the I-V characteristics. The results are in good agreement with computer simulation

The effects of n-well doping profile on the characteristics of SPT DRAM (substrate plate trench dynamic random access memory) data retention time are described and characterized. A retrograde n-well is shown to be desirable since it offers decreased well resistance without the modification of surface device characteristics. Retention time can be further improved with an n-well doping concentration that decreases monotically with increasing depth rather than a retrograde profile which has a doping peak below the silicon surface. An n-well with such a doping profile has superior median retention time and a reduced number of bits that fail a data retention test. This improvement has been demonstrated by the fabrication of 4-Mb SPT-cell DRAM arrays and test structures.<>

A (dynamic random-access memory) DRAM cell using a trench capacitor with a grounded substrate plate has been demonstrated, fabricated of functional fully decoded 64K arrays. The cell array is located inside the well and the trench capacitor extends from the planar surface through the well and epitaxial layer into the heavily doped substrate. The polysilicon inside the trench, connected to the source region of the transfer device, is used as the storage node and the bulk silicon surrounding the trench serves as the capacitor plate electrode. The cell features small area, high capacitance, small leakage current, low soft error rate, reduced surface topography, and a very stable capacitor-plate electrode. The arrays were fabricated in an advanced, 3.3-V, n-well epitaxial CMOS technology with a 15-nm gate insulator. The n- and p-channel transistors, exhibit transconductances of 120 and 650 mS/mm, respectively, at effective channel lengths of 6.0 /spl mu/m. Ring oscillators designed at this length have delays of 170 ps at 3.3 V.

Accurate prediction of device current and the capacitance to be driven by that current is key to the design of integrated logic and memory circuits. A finite-element algorithm is described which simulates the capacitance of structures with general shape in two or three dimensions. Efficient solution of the linear equations is provided by the incomplete Cholesky conjugate gradient method. The model is used to simulate the wiring capacitance of a 1.25-micrometer VLSI technology. The predicted capacitances of closely spaced first-metal polycide-gate and second-metal conductors used in this technology agree with measured results. The simulated three-dimensional capacitance of a second-metal line crossing a first-metal line is twice that found when estimated by two-dimensional models. The effect of line-to-line capacitance on the noise margin of logic circuits and on the signal in a dynamic RAM is examined. This capacitance presents a limit to wiring density for logic circuits and is a significant signal detractor in dynamic RAMs with closely spaced metal or diffused bit lines.

The FIELDAY program simulates semiconductor devices of arbitrary shape in one, two, or three dimensions operating under transient or steady-state conditions. A wide variety of physical effects, important in bipolar and field-effect transistors, can be modeled. The finite-element method transforms the continuum description of mobile carrier transport in a semiconductor device to a simulation model at a discrete number of points. Coupled and decoupled algorithms offer two methods of linearizing the differential equations. Direct techniques are used to solve the resulting matrix equations. Pre- and post-processors enable users to rapidly generate new models and analyze results. Specific examples illustrate the flexibility and accuracy of FIELDAY.

Mobile carrier transport in semiconductors, simulated in three dimensions, using the finite element method, will be reported. The algorithm has been used to model the combined effect of short channel lengths and narrow channel widths on the threshold of an IGFET.

This paper presents a channel hot-electron degradation model that is valid for both fixed and time-varying bias conditions. A simple relationship has been derived for the practical case of identical, repetitive pulses. The model uses gate current measurements of the emitted hot electrons to functionally relate FET structural parameters and bias conditions to the resulting threshold shift over time. Incorporated into circuit simulation programs, it has been used to predict long-term circuit behavior. Modeling results are given for the memory cell, word decoder, set latch driver, and sense amplifier drawn from a theoretical study of a 256-kbit dynamic RAM chip.