AlGaN/GaN high electron mobility transistors on QST engineered substrates are grown with different GaN/AlGaN buffer layer thickness. The as‐grown heterostructures are evaluated for their structural quality via atomic force microscopy, high‐resolution X‐ray diffraction, Raman spectroscopy, and steady‐state thermoreflectance. Transistor devices are fabricated and evaluated via DC and pulsed electrical techniques, as well as thermoreflectance imaging. It is reported that buffer layer thickness of at least 10 μm can result in lateral high electron mobility transistors (HEMTs) with simultaneously high GaN quality, low stress, good DC electrical performance, low current collapse, and low thermal resistance.

Metal-oxide-metal (MOM) devices based on niobium oxide exhibit threshold switching (or current-controlled negative differential resistance) due to thermally induced conductivity changes produced by Joule heating. A detailed understanding of the device characteristics therefore relies on an understanding of the thermal properties of the niobium oxide film and the MOM device structure. In this study, we use time-domain thermoreflectance to determine the thermal conductivity of amorphous NbOx films as a function of film composition and temperature. The thermal conductivity is shown to vary between 0.86 and 1.25 W·m-1·K-1 over the composition (x = 1.9 to 2.5) and temperature (293 to 453 K) ranges examined, and to increase with temperature for all compositions. The impact of these thermal conductivity variations on the quasistatic current-voltage (I-V) characteristics and oscillator dynamics of MOM devices is then investigated using a lumped-element circuit model. Understanding such effects is essential for engineering functional devices for nonvolatile memory and brain-inspired computing applications.

Gallium nitride (GaN) high electron mobility transistors (HEMTs) operate at high power levels and are thus especially thermally-critical devices. Not only do they require innovative thermal management strategies, but can also benefit from advanced experimental thermal characterization, both numerical and experimental, in their design and system integration stages. The thermal numerical analysis of microelectronic devices faces the challenges of complex physics and uncertain thermophysical properties which leads to numerically expensive models that are prone to error. By the use of an innovative reverse modeling approach to mitigate the above challenges, this work presents the full thermal characterization of GaN power devices with different substrates aimed at managing performance-limiting self-heating. The approach develops and optimizes a thermal simulation model to match the numerical results to experimentally-obtained thermal maps of the devices under test. The experimentally-optimized simulation model can then be used to extract full 3D temperature distributions, infer in-situ thermal properties, and provide a numerical platform that can be used to conduct further parametric studies and design iterations. The presented analysis provides a full thermal characterization of different GaN HEMT devices and compares the thermal performance of different substrates on the basis of thermal properties. The extracted properties for HEMTs on Si, SiC, and Diamond substrates are compared and a set of conclusions are presented to guide further developments in GaN HEMT thermal management strategies.

A compact 3D thermal model is developed for the quick and accurate thermal characterization of self-heating in Back-End-of-Line (BEoL) interconnect network for reliability assessment. The model offers a more accurate thermal tool compared to the currently used conservative 2D reduced models. Both 2D and 3D reduced models are developed and verified against numerical simulations of different configurations and further validated against thermoreflectance measurements of specially fabricated samples devices. The compact model ultimately provides quick thermal characterizations for vast ICT networks at a fraction of the analysis time and computational cost required for full numeric simulations, with improved accuracy that could reach 20 fold that of currently applied conservative reduced models. When integrated with electrical layout designs, the model would serve as a thermal check on VLSI and ULSI networks to identify thermally critical regions where overheating could lead to degradation and reliability issues.

The back-end components of integrated circuits (ICs) are susceptible to self-heating deteriorating effects due to the microscale interconnects carrying large current densities, and thus require innovative passive cooling strategies. This article investigates the cooling effect of the high conductivity metallization (MET) fill that is used in conjunction with the chemical mechanical planarization (CMP) process. Thermal simulation models are developed for a three-level back end of line (BEOL) stack and then validated experimentally using high-resolution thermal imaging. A coupled approach is used to optimize the numerical model and fully characterize the BEOL embedded passive cooling solution. Results indicate that stricter thermal constraints are present for devices higher in the BEOL stack and exhibit the highest cooling potential from the use of CMP fill in the underlying MET layers. As a thermal improvement strategy for such thermally critical interconnects, a CMP fill-based cooling solution is presented by modifying the fill pattern in order to maximize heat dissipation within the BEOL. The resulting heat spreader (HS) design achieved up to 30% reduction in temperature for 10-mu m-wide interconnects and can reach 43% for narrower interconnects. The gained cooling makes it possible to extend the activation limits of interconnects by 15% and 25%, respectively. The experimentally validated HS simulation model is used to conduct parametric analysis for a range of interconnect dimensions with an eye on standardizing the HS design within the BEOL stage of ICs.

This article presents an electric-based methodology for thermal characterization of semiconductor technologies. It is shown that for technologies such as gallium nitride (GaN) high electron mobility transistors, which exhibit several field induced electron trapping effects, the thermal characterization has to be performed under specific conditions. The electric field is limited to low levels to avoid activation of trap states. At the same time, the dissipated power needs to be high enough to change the operating temperature of the device. The method is demonstrated on a test structure implemented as a GaN resistor with large contact separation. It is used to evaluate the thermal properties of samples with different silicon carbide suppliers and buffer thickness.

The negative differential resistance (NDR) response of Nb/NbOx/Pt cross-point devices is shown to have a polarity dependence due to the effect of the metal/oxide Schottky barriers on the contact resistance. Three distinct responses are observed under opposite polarity testing: bipolar S-type NDR, bipolar snap-back NDR, and combined S-type and snap-back NDR, depending on the stoichiometry of the oxide film and device area. In-situ thermoreflectance imaging is used to show that these NDR responses are associated with strong current localisation, thereby justifying the use of a previously developed two-zone, core shell thermal model of the device. The observed polarity dependent NDR responses, and their dependence on stoichiometry and area are then explained by extending this model to include the effect of the polarity dependent contact resistance. This study provides an improved understanding of the NDR response of metal/oxide/metal structures and informs the engineering of devices for neuromorphic computing and non-volatile memory applications.

Gallium nitride (GaN) high electron-mobility transistors (HEMTs) offer considerable high-power operation but suffer in reliability due to potentially damaging self-heating. In this study, self-heating in AlGaN/GaN HEMTs on high conductivity substrates is assessed using a high-resolution thermoreflectance (TR) imaging technique, to compare the thermal response between GaN-on-Si, GaNon-Diamond, and GaN-on-4H-SiC. The TR method accuracy at high-power density is verified using a nonlinear coefficient of TR (CTR) as a function of temperature. The acquired steady-state thermal maps give a thermal resistance of 11.5 mm · K/W for GaN-on-Si (based on peak channel temperature), compared to 2.7 and 3.3 mm · K/W for GaN-on-SiC and GaN-on-diamond substrates, respectively. The tested GaN-on-diamond HEMT exhibits similar heating rates to those seen on a SiC substrate, with a slightly higher peak temperature, which indicates a higher thermal boundary resistance that could offset the benefits of using a higher conductivity substrate and lead to faster thermally enhanced degradation. The analysis reveals the importance using high-resolution imaging to detect hotspots and areas of peak temperature that largely affect failure initiation and device reliability and which may not be otherwise observable.

There are continuing rapid developments in vertical geometry Ga2O3 for high voltage switching applications. Ga2O3 is emerging as a viable candidate for certain classes of power electronics with capabilities beyond existing technologies due to its large bandgap, controllable doping and the availability of large diameter, relatively inexpensive substrates. These include power conditioning systems, including pulsed power for avionics and electric ships, solid-state drivers for heavy electric motors and advanced power management and control electronics. There are already cases where the performance exceeds the theoretical values for SiC. Existing Si, SiC (vertical devices), and heteroepitaxial GaN (lateral devices) enjoy tremendous advantages in terms of process maturity, an advantage that is especially true for Si, where the ability to precisely process the material has resulted in devices such as super-junctions that surpass the unipolar “limit”. Continued development of low defect substrates, optimized epi growth and surface treatments and improved device design and processing methods for Ga2O3 are still required to push the experimental results closer to their theoretical values. Even 3 μm epi layers with doping concentration of 1016 cm-3 should have a theoretical breakdown voltage of ~1800V. The actual experimental value of VB is currently well below the theoretical predictions. Thermal management is a key issue in Ga2O3 power devices for practical high current devices and initial studies have appeared on both the experimental and theoretical fronts. We summarize progress in edge termination design, temperature measurement using thermoreflectance-based thermography to measure the thermal rise and decay of the active diodes, failure under forward bias and development of large current (up to 130A) arrays.

Gallium Nitride (GaN) based high-power devices require advance thermal analysis to ensure that the operating temperature is kept within a reliable range. High conductivity substrates such as Silicon Carbide (SiC) are used instead of Silicon (Si) to increase the thermal conductance from the device structure. This study observes the self-heating in GaN-SiC HEMTs using high-resolution thermoreflectance imaging. A verification with multi-grid self-adaptive modeling shows a dynamic power generation profile that changes from low to high activation levels. The method allows to estimate the heat generation profile in the GaN HEMT from the observed temperature rise profile across the GaN channel, which is crucial to understand the heat generation regime and develop an accurate thermal model for the GaN HEMTs.

Electroforming is used to initiate the memristive response in metal/oxide/metal devices by creating a filamentary conduction path in the oxide film. Here, we use a simple photoresist-based detection technique to map the spatial distribution of conductive filaments formed in Nb/NbOx/Pt devices, and correlate these with current-voltage characteristics and in situ thermoreflectance measurements to identify distinct modes of electroforming in low- and high-conductivity NbOx films. In low-conductivity films, the filaments are randomly distributed within the oxide film, consistent with a field-induced weakest-link mechanism, while in high-conductivity films they are concentrated in the center of the film. In the latter case, the current-voltage characteristics and in situ thermoreflectance imaging show that electroforming is associated with current bifurcation into regions of low and high current density. This is supported by finite element modeling of the current distribution and shown to be consistent with predictions of a simple core-shell model of the current distribution. These results clearly demonstrate two distinct modes of electroforming in the same material system and show that the dominant mode depends on the conductivity of the film, with field-induced electroforming dominant in low-conductivity films and current bifurcation-induced electroforming dominant in high-conductivity films.

GaN HEMT devices with source-connected field-plates are characterized thermally to quantify their performance. A Thermoreflectance approach is used to obtain surface temperature maps of the unobstructed GaN junction areas. Different temperature behaviors on different power levels are found. In addition, a 3D thermal model is used to simulate the temperature distribution of the device. The simulation results show good correspondence with the experimental data.

Record DC power has been demonstrated in AlGaN/GaN high electron mobility transistors fabricated using a substrate replacement process in which a thick diamond substrate is grown by chemical vapor deposition following removal of the original Si substrate. Crucial to the process is a ~30 nm thick SiN interlayer that has been optimized for thermal resistance. The reductions obtained in self-heating have been quantified by transient thermoreflectance imaging and interpreted using 3D numerical simulation. With a DC power dissipation level of 56 W/mm, the measured average and maximum temperatures in the gate-drain access region were 176 °C, and 205 °C, respectively.

In-situ thermo-reflectance imaging is used to show that the discontinuous, snap-back mode of current-controlled negative differential resistance (CC-NDR) in NbOx-based devices is a direct consequence of current localization and redistribution. Current localisation is shown to result from the creation of a conductive filament either during electroforming or from current bifurcation due to the super-linear temperature dependence of the film conductivity. The snap-back response then arises from current redistribution between regions of low and high current-density due to the rapid increase in conductivity created within the high current density region. This redistribution is further shown to depend on the relative resistance of the low current-density region with the characteristics of NbOx cross-point devices transitioning between continuous and discontinuous snap-back modes at critical values of film conductivity, area, thickness and temperature, as predicted. These results clearly demonstrate that snap-back is a generic response that arises from current localization and redistribution within the oxide film rather than a material-specific phase transition, thus resolving a long-standing controversy.

Alternating current electrothermal flow (ACET) induced by Joule heating is utilized to transport biologically relevant liquids in microchannels using simple electrode designs. However, Joule heating may cause significant temperature rises, which can degrade biological species, and hence, ACET may become impractical for biomicrofluidic sensors and other possible applications. In this study, the temperature rise at the electrode/electrolyte interface during ACET flow is measured using a high-resolution, noninvasive, thermoreflectance imaging method, which is generally utilized in microelectronics thermal imaging applications. The experimental findings reveal that Joule heating could result in an excessive temperature rise, exceeding 50 °C at higher voltage levels (20 Vpp). The measured data are compared with the results of the enhanced ACET theoretical model, which predicts the temperature rise accurately, even at high levels of applied voltages. Overall, our study provides a temperature measurement technique that is used for the first time for electrode/electrolyte systems. The reported results are critical in designing biomicrofluidic systems with significant energy dissipation in conductive fluids.

There are continuing rapid developments in vertical geometry Ga2O3 for high voltage switching applications. Ga2O3 is emerging as a viable candidate for certain classes of power electronics with capabilities beyond existing technologies due to its large bandgap, controllable doping and the availability of large diameter, relatively inexpensive substrates. These applications include power conditioning systems, including pulsed power for avionics and electric ships, solid-state drivers for heavy electric motors and advanced power management and control electronics.There are already cases where the performance exceeds the theoretical values for SiC. Existing Si, SiC (vertical devices), and heteroepitaxial GaN (lateral devices) enjoy tremendous advantages in terms of process maturity, an advantage that is especially true for Si, where the ability to precisely process the material has resulted in devices such as super-junctions that surpass the unipolar “limit”. Despite these challenges, a compelling case can be made for investigation of UWBG materials. Continued development of low defect substrates, optimized epi growth and surface treatments and improved device design and processing methods for Ga2O3 are still required to push the experimental results closer to their theoretical values. Even 3 µm epi layers with doping concentration of 1016 cm-3 should have a theoretical breakdown voltage of ~1800V. The actual experimental value of VB is currently well below the theoretical predictions. Thermal management is a key issue in Ga2O3 power devices and initial studies have appeared on both the experimental and theoretical fronts. We will summarize progress in edge termination design, temperature measurement using thermoreflectance-based thermography to measure the thermal rise and decay of the active diodes, reverse recovery switching times and develop of large current arrays.

There is increasing adoption of SiC and GaN for various high-power applications, including in the areas of transportation, electricity production and distribution, control of industrial machinery, and military systems. These applications are expanding the market for wide bandgap materials beyond the existing important uses in chargers for smartphones, laptops, and television sets. The primary attraction of wide bandgap semiconductors is their ability to deliver higher power density and better efficiency as compared to equivalent devices made with silicon. Wide bandgap materials, such as SiC, GaN, and Ga2O3 can also withstand much higher temperatures, thus reducing the need for costly cooling systems. A major drawback of Ga2O3 as compared to other candidate semiconductors is its low thermal conductivity. This apparent limitation could potentially be mitigated by transferring devices to other substrates as has already been demonstrated for GaN, and/or by using heat spreaders and even top-side heat extraction. At present, the electrical performance of Ga2O3 rectifiers is limited by the presence of defects and by lower than desired breakdown voltage initiated in the depletion region near the electrode corners. In the more established SiC and GaN rectifier technologies, these shortcomings are mitigated by the use of edge termination methods whose effect is to smooth out the electric field distribution around the rectifying contact periphery. Such methods have included field plates and ion-implanted high-resistivity layers. But the recent success in producing Ga2O3 bulk wafers as well as doped epitaxial layers grown on these wafers are promising developments for power device applications of Ga2O3, especially vertical geometry rectifiers. So, if continued efforts can be successful in minimizing the on-state resistance Ron while increasing the breakdown voltage, Ga2O3-based devices can extend power switching to voltages above those possible with SiC and GaN. The thermal behavior of such devices is not only an important gage of electrical performance, but can also serve as an early indicator of the onset of failure, both spatially and temporally. Therefore, in this work, we set out to report on the thermal performance of edge-terminated, vertical geometry, Schottky diode devices. By using thermoreflectance-based thermography, we were able to map the temperature distribution on the surface of a diode with deep submicron resolutions. We also pulse activated the diodes with various prescribed periods and duty cycles, and tracked their thermal response by capturing the surface temperature fields at different times within each activation period. In doing so, we were able to resolve the thermal rise and decay of the active diodes. The attached figure shows an example of the temperature map obtained on the surface of a 100-µm Ga2O3 Schottky diode. The device under test is shown on the left side of the image while on the right side, the temperature rise field is shown just before the device is turned off. The line plot on the bottom left side shows the average temperature in the center of the device at different time points within the 5-second period that the shown device was pulsed at. Figure 1

Record DC power has been demonstrated in AlGaN/GaN high electron mobility transistors fabricated using a substrate replacement process in which a thick diamond substrate is grown by chemical vapor deposition following removal of the original Si substrate. Crucial to the process is a ~30 nm thick SiN interlayer that has been optimized for thermal resistance. The reductions obtained in self-heating have been quantified by transient thermoreflectance imaging and interpreted using 3D numerical simulation. With a DC power dissipation level of 56 W/mm, the measured average and maximum temperatures in the gate-drain access region were 176 °C and 205 °C, respectively.