When designing arithmetic circuits, the multiplication of a variable by a constant number can be performed by a series of add/subtract, and shift operations instead of a multiplication (e.g., 7x = 2(3)x-x = (x << 3)-x). This allows for significant reductions in complexity of multiplication circuits, as adders are typically much more hardware-efficient than a generic multiplier, and shift operations can be performed without any overhead by appropriately connecting the concerned signals. This concept extends to the multiplication of a constant matrix by a vector of variables, known as constant matrix multiplication (CMM). So far, there exists no way of discovering CMM algorithms with provably minimal add/subtract count. Here, we show how the CMM problem can be reduced to a series of Boolean satisfiability (SAT) problems, enabling the use of powerful SAT solvers to determine optimal solutions for arbitrary matrices. Modeling the problem in a closed mathematical framework allows us to straightforwardly extend our algorithm toward secondary objectives, namely word-size reductions of the add/subtract operations and pipelining for throughput maximization. Compared to state-of-the-art heuristic methods, we were consistently able to achieve improvements regarding the resulting implementation complexity, even for small but practical matrix sizes such as 2 & times; 2 or 3 & times; 3. These results enable a reduction in implementation costs for a wide range of practical applications such as digital filters, convolutional cores in artificial neural networks, or the multiplication by complex constants in discrete transforms like the fast Fourier transform.

Modulo scheduling is a highly effective approach for maximizing throughput in loops with static memory dependencies, interleaving computations across consecutive loop iterations. Despite substantial advancements in scheduling procedures, it remains the most computationally intensive phase for high-level synthesis flows. A recent approach encodes the modulo scheduling problem as a series of Boolean satisfiability (SAT) instances, capitalizing on the efficiency of modern SAT solvers. This approach significantly reduces solving time and increases the availability of throughput-optimal solutions compared to integer linear programming-based algorithms. This work introduces two enhancements for SAT-based modulo scheduling: (i) an algorithm to rapidly calculate a lower bound for the schedule length, improving the identification of latency-optimal schedules; and (ii) a streamlined SAT formulation with fewer clauses, facilitating quicker solver decisions. Extensive experimental evaluations show that these improvements lead to an increased number of throughput-optimal and latency-optimal solutions.

Multiplexers (MUX) are essential elements in FieldProgrammable Gate Arrays (FPGA), widely used in practical applications. Due to the LUT-based architecture of FPGAs, multiplexers that switch among many signals or operate on large word sizes incur significant resource costs, as these costs scale linearly with the data word size. Vivado's automatic synthesis flow often produces sub-optimal MUX implementations, necessitating hand-crafted solutions to minimize resource overhead. Here, we present three MUX implementation schemes that reduce resource usage for various input signal counts. These optimizations enable enhanced resource efficiency in applications ranging from circuits generated by High-Level Synthesis (HLS) tools to optimized digital filters and artificial neural networks.

The end of Moore’s law and Dennard scaling emphasizes the need for application-specific computing architectures to achieve high resource and energy efficiency and real-time performance. The concept of a silicon compiler remains an enduring aspiration for design time reduction. In order to generate hardware implementations at register transfer level from behavioral descriptions, design automation tools must address challenging and interdependent problems, including allocation, scheduling, and binding. Additionally, manual intervention by the user is necessary to balance the resources vs. performance tradeoff via, for example, function inlining or loop unrolling/pipelining. Existing approaches typically solve these problems sequentially, compromising optimality in favor of simplicity and runtime. Here we show how to model the whole model-based design flow as one holistic integer linear programming (ILP) formulation aiming at consistently deriving the optimal microarchitecture for any given application. Incorporating clock gating minimizes the number of useless operations with negligible resource overhead (if any), while always guaranteeing optimal throughput. The unified nature of the proposed ILP model enables implementations unmatched by state-of-the-art approaches in terms of resource efficiency and measured power consumption. These results facilitate a streamlined design flow for highly optimized embedded systems in the context of model-based design.

Multiplierless constant multiplication using bit-shifts, additions and subtractions has been an active research topic in the last decades. The multiplication with multiple constants, known as the multiple constant multiplication (MCM) problem, is of special interest because of its practical relevance, notably for digital filter implementation. In this work we propose to use the speed of modern Boolean satisfiability (SAT) solvers to find fast and optimal solutions. The solutions are optimal either with respect to the adder count or the bit level cost. In contrast to previous approaches, we also consider negative fundamentals that are sometimes cheaper to realize than their positive counterparts leading to more compact hardware implementations. Our experiments show that our approach is able to find optimal single constant multiplication (SCM) and MCM circuits for practically relevant test instances in reasonable time. We also prove the necessity for the post-add right shift operation for SCM. Using our SAT formulation to enumerate all possible implementations for some of our test instances we show the importance of considering bit-level costs and negative fundamentals when solving MCM problems.

Modulo scheduling is the premier technique for throughput maximization of loops in high-level synthesis by interleaving consecutive loop iterations. The number of clock cycles between data insertions is called the initiation interval (II). For throughput maximization, this value should be as low as possible; therefore, its minimization is the main optimization goal. Despite its long historical existence, modulo scheduling always remained a relevant research topic over the years with many exact and heuristic algorithms available in the literature. Nevertheless, we are able to leverage the scalability of modern Boolean Satisfiability (SAT) solvers to outperform state-of-the-art ILP-based algorithms for latency-optimal modulo scheduling for both integer and rational IIs. Our algorithm is able to compute valid modulo schedules for the whole CHStone and MachSuite benchmark suites, with 99% of the solutions being proven to be throughput optimal for a timeout of only 10 minutes per candidate II. For various time limits, not a single tested scheduler from the state of the art is able to compute more verified optimal solutions or even a single schedule with a higher throughput than our proposed approach. Using an HLS toolflow, we show that our algorithm can be effectively used to generate Pareto-optimal FPGA implementations regarding throughput and resource usage.

We present a training tool flow for deep neural networks (DNN) optimized for a hardware-efficient FPGA-implementation based on reconfigurable constant-coefficient multipliers (RCCMs). RCCMs replace the costly generic multipliers by shift-and-add operations. In previous work, it was shown that RCCMs offer a better alternative for saving FPGA area than utilizing low-precision arithmetic. This work proposes an improved tool flow that enables layer-wise weight quantization, a larger search space by additional RCCM coefficient sets and an optimized retraining. This leads to an improved accuracy compared to the previous method. In addition, hardware requirements are lower as only 1 to 3 adders per multiplication are used. This reduces the overall complexity and the required memory bandwidth simultaneously. We evaluate our tool flow using multiple networks (ResNets) on the ImageNet data set.

Modulo scheduling is a commonly used high-level synthesis (HLS) technique to maximize throughput by overlapping the computation of consecutive loop iterations [1] – [5] . For maximum throughput, the number of cycles to wait between successive sample insertions (called initiation interval, II) should be as low as possible.

In order to provide high throughput for custom hardware implementations, academic and commercial high-level synthesis (HLS) tools use loop pipelining by modulo scheduling. When provided a resource allocation and a schedule, the binding algorithm can be used to reduce the number of required lifetime registers (LR) and multiplexers (MUX). Contrary to non-modulo schedules, optimal solutions to the binding problem for implementing modulo schedules with respect to minimizing required LRs and MUXs have not been published. To address this topic, we propose a novel optimal binding algorithm to simultaneously minimize MUX and LR costs for loop pipelining using Integer Linear Programming. We evaluated our algorithm on a set of commonly used benchmark instances from digital signal processing and report that all encountered problems could be solved, with 36.53% of the solutions being optimal within a time limit of only five minutes. Compared to worst case evaluations, we report MUX and LR savings of up to 42.74% and 26.62%, respectively. To evaluate the impact on the resulting circuit after place and route, we studied FPGA implementations of several benchmark instances and recorded look-up table and flip-flop reductions of up to 13.70% and 5.24%, respectively, compared to previous work and to an extensive set of randomly generated bindings when state-of-the-art algorithms fail to find a feasible solution.

Compared to integer initiation intervals (II), rational IIs improve throughput achieved by loop pipelining in many cases. This comes at the expense of a higher need for data path elements (i.e., multiplexers and registers) and the need for solving more complex scheduling problems. To optimally solve these problems, we improved an existing ILP formulation for latency-optimal modulo scheduling with rational IIs that now finds 6.08x more solutions and 6.10x as many optimal ones within the same time budget. Compared to the best alternative from previous work, our improved algorithm finds 1.15x more solutions and 2.97x as many optimal ones.

A well-known approach for generating custom hardware with high throughput and low resource usage is modulo scheduling , in which the number of clock cycles between successive inputs [the initiation interval (II)] can be lower than the latency of the computation. The II is traditionally an integer , but in this article, we explore the benefits of allowing it to be a rational number. A rational II can be interpreted as the average number of clock cycles between successive inputs. Since the minimum rational II can be less than the minimum integer II, higher throughput is possible; moreover, allowing rational IIs gives more options in a design-space exploration. We formulate rational-II modulo scheduling as an integer linear programming (ILP) problem that is able to find latency-optimal schedules for a fixed rational II. We also propose two heuristic approaches that make rational-II scheduling more feasible: one based on identifying strongly connected components in the data-flow graph, and one based on iteratively relaxing the target II until a solution is found. We have applied our methods to a standard benchmark of hardware designs, and our results demonstrate an average speedup with respect to II of $1.24\times $ in 35% of the encountered scheduling problems compared to state-of-the-art formulations.

The development of new electric traction machines requires a complex process of experimentation due to the many factors that affect motor performance. Dedicated test benches, which are complex and vulnerable to failures during experiments, generate heterogeneous multivariate time series data collected by multiple sensors. Failures or anomalous states in these systems can slow down the development and testing process enormously. This article proposes a new and innovative approach to machine-learning-empowered monitoring and predictive maintenance for motor test benches. It allows to optimize the test process and reduce costly test bench downtime, with a self-improvement cycle to respond to new operation areas during run-time, integration of new components, continuous knowledge integration of human operators, autonomous parameter updating of machine-learning models, and hardware accelerated monitoring. Based on a first case study, we show that our procedure produces promising results based on the raw data for failure detection and failure type classification, representing an essential block of self-awareness in the system. A dedicated hardware-accelerated machine-learning online monitoring allows to meet critical time constraints and optimise power consumption. In a second case study, we demonstrate automated word-width reductions, which results in a smaller implementation of the network and reduce the needed memory bandwidth. All by keeping floating point accuracy and taking reconfigurable constant coefficient multiplication instead of generic multiplication into account.

In modulo scheduling, the number of clock cycles between successive inputs (the initiation interval, II) is traditionally an integer, but in this paper, we explore the benefits of allowing it to be a rational number. This rational II can be interpreted as the average number of clock cycles between successive inputs. As the minimum rational II can be less than the minimum integer II, this translates to higher throughput. We formulate rational-II modulo scheduling as an integer linear programming (ILP) problem that is able to find latency-optimal schedules for a fixed rational II. We have applied our scheduler to a standard benchmark of hardware designs, and our results demonstrate a significant speedup compared to state-of-the-art integer-II and rational-II formulations.

Low-precision arithmetic operations to accelerate deep-learning applications on field-programmable gate arrays (FPGAs) have been studied extensively, because they offer the potential to save silicon area or increase throughput. However, these benefits come at the cost of a decrease in accuracy. In this article, we demonstrate that reconfigurable constant coefficient multipliers (RCCMs) offer a better alternative for saving the silicon area than utilizing low-precision arithmetic. RCCMs multiply input values by a restricted choice of coefficients using only adders, subtractors, bit shifts, and multiplexers (MUXes), meaning that they can be heavily optimized for FPGAs. We propose a family of RCCMs tailored to FPGA logic elements to ensure their efficient utilization. To minimize information loss from quantization, we then develop novel training techniques that map the possible coefficient representations of the RCCMs to neural network weight parameter distributions. This enables the usage of the RCCMs in hardware, while maintaining high accuracy. We demonstrate the benefits of these techniques using AlexNet, ResNet-18, and ResNet-50 networks. The resulting implementations achieve up to 50% resource savings over traditional 8-bit quantized networks, translating to significant speedups and power savings. Our RCCM with the lowest resource requirements exceeds 6-bit fixed point accuracy, while all other implementations with RCCMs achieve at least similar accuracy to an 8-bit uniformly quantized design, while achieving significant resource savings.

Convolutional neural networks (CNNs) gained great success in machine learning applications and much attention was paid to their acceleration on field programmable gate arrays (FPGAs). The most demanding computational complexity of CNNs is found in the convolutional layers, which account for 90% of the total operations. The fact that parameters in convolutional layers do not change over a long time interval in weight stationary CNNs allows the use of reconfiguration to reduce the resource requirements. This work proposes several alternative reconfiguration schemes that significantly reduce the complexity of sum-of-products operations. The proposed direct configuration schemes provide the least resource requirements and fast reconfiguration times of 32 clock cycles but require additional memory for the pre-computed configurations. The proposed online reconfiguration scheme uses an online computation of the LUT contents to avoid this memory overhead. Finally, a scheme that duplicates the reconfigurable LUTs is proposed for which the reconfiguration time can be completely hidden in the computation time. Combined with a few online reconfiguration circuits, this provides the same configuration memory and configuration time as a conventional parallel kernel but offers large resource reductions of up to 80% of the LUTs.

The computational complexity of neural networks for large-scale or real-time applications necessitates hardware acceleration. Most approaches assume that the network architecture and parameters are unknown at design time, permitting usage in a large number of applications. This article demonstrates, for the case where the neural network architecture and ternary weight values are known a priori , that extremely high throughput implementations of neural network inference can be made by customising the datapath and routing to remove unnecessary computations and data movement. This approach is ideally suited to FPGA implementations as a specialized implementation of a trained network improves efficiency while still retaining generality with the reconfigurability of an FPGA. A VGG-style network with ternary weights and fixed point activations is implemented for the CIFAR10 dataset on Amazon’s AWS F1 instance. This article demonstrates how to remove 90% of the operations in convolutional layers by exploiting sparsity and compile-time optimizations. The implementation in hardware achieves 90.9 ± 0.1% accuracy and 122k frames per second, with a latency of only 29µs, which is the fastest CNN inference implementation reported so far on an FPGA.

Today, the design of hardware implementations using FPGAs, SoCs or ASICs is driven by tight project time and cost constraints. Additionally, it is impossible to specify every step and functionality of a complex project beforehand. Therefore, large teams from different areas of expertise, e.g., software, hardware development, system integration, need to work hand in hand as they are confronted with an ever changing environment of specifications. Detailed simulations and prototyping are used to keep track of the project status and for the identification of failed developments as early as possible. Over the recent years, high-level synthesis (HLS) is used more and more for hardware design. Unfortunately, run times can become very long when close to optimal implementations are demanded. It follows that an inflexible HLS design flow is not applicable for large, complex and changing projects. With the open-source C++ scheduling library HatScheT we provide a tool for run time flexible scheduling, which is the most important and time consuming step of HLS. The user of HatScheT is able to chose from a variety of scheduling algorithms, which enables control over a scheduling run time vs. quality tradeoff. Additionally, an adaptive decider program is presented that will automatically chose one from a set of scheduling algorithms based on the size of the input problem. This enables a flexible scheduling flow, where optimal algorithms are applied when a low complexity is identified, while heuristics are chosen for large and time consuming scheduling problems.

Constant matrix multiplication (CMM), i.e., the multiplication of a constant matrix with a vector, is a common operation in digital signal processing. The CMM operation can be realized multiplierless using only additions/subtractions and bit shifts. Modern FPGAs support the efficient mapping of ternary adders, i.e., adders with three inputs. Previous work has shown that the usage of ternary adders for the FPGA implementation of other multiplierless constant multiplication problems is very beneficial. However, no algorithm exists to optimize CMM operations with ternary adders. This work proposes a novel heuristic approach to further reduce CMM complexity for FPGAs by exploiting ternary adders. The algorithm can be targeted for combinatorial CMM with minimal depth or fully pipelined CMM operations. It is shown experimentally that 30% less operations are needed on average by using ternary adders, resulting in 11% LUT reductions.

This work presents an extension of Karatsuba's method to efficiently use rectangular multipliers as a base for larger multipliers. The rectangular multipliers that motivate this work are the embedded 18 × 25-bit signed multipliers found in the DSP blocks of recent Xilinx FPGAs: The traditional Karatsuba approach must under-use them as square 18 × 18 ones. This work shows that rectangular multipliers can be efficiently exploited in a modified Karatsuba method if their input word sizes have a large greatest common divider. In the Xilinx FPG A case, this can be obtained by using the embedded multipliers as 16 × 24 unsigned and as 17 × 25 signed ones. The obtained architectures are implemented with due detail to architectural features such as the pre-adders and post-adders available in Xilinx DSP blocks. They are synthesized and compared with traditional Karatsuba, but also with (non-Karatsuba) state-of-the-art tiling techniques that make use of the full rectangular multipliers. The proposed technique improves resource consumption and performance for multipliers of numbers larger than 64 bits.