In this work, the design of a linear Mach-Zehnder modulator driver for coherent optical communications is presented. The design, based on transconductor-transimpedance closed-loop topologies, achieves very low distortion, opening the way to the use of complex modulation formats. The measured Total Harmonic Distortion (THD) for 1.5 V peak-to-peak differential (V-ppd) output swing at 1 GHz is 0.85 %, with a -3 dB bandwidth of 33 GHz and a continuously-programmable gain ranging from 10 dB to 20 dB. The overall power consumption is 204 mW, with a single supply voltage of 2.4 V. The chip has been fabricated in 28 nm CMOS technology, demonstrating the feasibility of both high performances, greater integration, and lower costs.

A direct conversion receiver front-end with frequency-translated positive feedback is presented in this paper. The forward path includes a low-noise transconductance amplifier, four-phase passive mixers and 3-rd order filtering transimpedance amplifiers. A tunable RC feedback path is attached at the baseband output, followed by an additional fourphase passive up-conversion mixers, allowing tunable, frequencyselective input matching. An on-chip frequency divider provides quadrature LO waveforms with a 25% duty cycle and no overlap. The receiver is fabricated in 28 nm CMOS technology and operates between 2 and 2.8 GHz, has an RF bandwidth of 28 MHz, more than 40 dB gain, and a Noise Figure of 3 to 3.4 dB. Out-of-band IIP3 and 1-dB blocker compression are 18 dBm and -2dBm respectively. The receiver core consumes 37mW.

In this work we present a wide-band amplifier that uses a novel analog pre-distioriton technique based on the quantized-analog (QA) signal processing. Such a technique is exploited to reach an almost rail-to-rail output swing with low distortion compatible with optical driver applications. Based on post layout simulations a 36 GHz −3 dB bandwidth prototype, integrated in 28 nm CMOS technology, shows a 3% Total Harmonic Distortion for 2 V peak-to-peak differential output swing at 1 GHz. The circuit operates under a 1.2 V supply voltage with a dynamic power consumption of 152 mW.

This work presents wide-band/wide range Variable Gain Amplifier (VGA) based on the Quantized-Analog (QA) processing. The VGA is formed by an array of sub-units that amplify different portions of the input signal. The gain variation is obtained by acting on the signal correlation among adjacent slices that are eventually recombined on an output load. The VGA has been characterized, by inserting the VGA inside an optical RF front-end which includes a TIA stage and output buffer. Designed and layouted in 28nm CMOS, the VGA shows a gain variation of about 22 dB obtained in one stage, and a -3dB bandwidth of 29 GHz. At maximum gain, the average equivalent input-referred current noise is equal to 10.3 pA/$\sqrt{Hz}$ while the Total Harmonic Distortion (THD) is below 2.3% for a maximum output swing of 500-mV peak-to-peak differential. The VGA consumes 64 mW while the complete front-end 124 mW from a 1.2V voltage supply.

An auxiliary receiver is proposed, including a high dynamic range low-noise amplifier and second-order baseband filter to improve the compression point with low power dissipation. The receiver has high input impedance and it can be placed at the transmitter output without loading effects. Implemented in a 28nm CMOS technology it occupies an active area of 0.5 mm(2). The receiver has a measured NF of 6 dB and it can withstand up to +7 dBm continuous waveform (CW) signal at 80 MHz offset with less than 1-dB gain compression. The signal path and the clock generation circuits consume 27 mW and 20 mW at 2 GHz respectively.

Trans-impedance amplifiers (TIAs) are used as building blocks in many applications: from wireless transceivers to qubit manipulation and readout in quantum computing [1] or as amplifying circuits in fiber optics receivers [2].

This work reports on a low-intermediate frequency (IF) voltage-mode receiver front-end for Internet-of-Things (IoT) applications. Design and noise analysis of an unbalanced gate-boosted common-gate low-noise amplifier (LNA) is presented, showing 50% lower power dissipation compared with the conventional balanced topology. Improved linearity is achieved thanks to channel-selection, consisting of two complex poles centered at 2 MHz IF. The first complex pole is embedded in the passive down-conversion mixer for improved frequency selectivity in front of the baseband voltage amplifier. Built in a 28-nm CMOS process, the proposed front-end occupies an active area of 0.175 mm 2 , it is supplied with 1 V and consumes only 400 $\mu \text{W}$ , while showing a minimum noise figure (NF) of 6.8 dB and an out-of-band (OOB) IIP 3 of −0.35 dBm. The performance meets Bluetooth low-energy (BLE) requirements and is competitive with other sub-mW receivers.

During my research life I witness 40 years of CMOS analog design. I was lucky to be at U.C. Berkeley when all this started, and my Ph.D. with Prof. Paul Gray was part of it. I kept my focus on analog CMOS at the University of Pavia even if the migration toward digital and the dream of analog design automation decreased the interest on it. CMOS circuits moved from audio to THz as the technology scaled three orders of magnitude. This talk will show this amazing evolution with some example circuit and system primarily for RF but not only. I will look from both academia and industry presenting device, circuit and architectural innovations. I hope this talk can bring motivation to younger researchers to drive the next CMOS developments.

This work presents a linear Mach-Zenhder mod-ulator driver. The key features of this design are a distortion which goes with the inverse of the input amplitude and a wide bandwidth. The two things make the reported driver suitable for Coherent Optical Applications. The mainstream technology for these applications is BiCMOS, however, in this case, a 28 nm CMOS technology has been used, aiming for higher integration level and lower cost. The resulting Total Harmonic Distortion (THD) for 1.5 V peak-to-peak differential output swing is always below 1.8%, with a -3 dB bandwidth of 58 GHz. The complete transmitter provides gain ranging from 10 dB to 20 dB in a continuous way. The overall power consumption at 20 dB is 297 mW, with a single supply voltage of 2.4 V.

A transimpedance amplifier (TIA) is presented for 5G and future mobile standards. The bandwidth of the TIA can be programmed from 500 MHz to 1.5 GHz. The operational transconductance amplifier (OTA) is designed combining feedforward compensation and inductive peaking, to ensure loop stability and obtain high loop gain with low-power dissipation. TSMC 28-nm HPC technology was used to implement a test chip. With a power dissipation of 17 mW, the TIA achieves an in-band IIP3 ranging from 35 to 42 dBm and output integrated noise of 300 $\mu $ Vrms.

Internet-of-Things (IoT) and Wireless sensor networks (WSNs) require very low power transceivers. This paper presents techniques for minimizing power consumption of receiver (RX) frontends for short range wireless links. Two key approaches, i.e., current reuse and supply voltage reduction are compared. Different RX architectures such as direct-conversion, low-IF, sliding IF as well as phase-tracking RX, are compared, emphasizing their potential and limitations when targeting sub-mW RX power dissipation. Low-power design techniques for LNA, frequency generation blocks and baseband amplifiers are presented. As a case study, an efficient low-IF RX front-end for IoT is described in detail. In 28 nm CMOS, such a receiver occupies an active area of 0.1 mm2 and consumes only $350~{\mu }\text{W}$ from a 0.9 V supply while showing a minimum in band NF of 6.2 dB. The achieved performance is very competitive with state-of-the-art ultra-low-power receivers, while consuming the lowest power.

This work reports on a low-intermediate frequency (IF) receiver front-end for Internet-of-Things applications. An un-balanced gate-boosted common-gate low-noise amplifier is proposed with 50% lower power dissipation compared with the conventional balanced topology. Channel-selection is performed with 2 complex poles centered at 2 MHz IF. The first complex pole is embedded in the passive down-conversion mixer, enabling higher in-band voltage gain and improved frequency selectivity. Built in a 28-nm CMOS process, the proposed front-end occupies an active area of 0.175 mm 2 , it is supplied with 1 V and consumes only 400 µW, while showing a minimum NF of 6.8 dB and an out-of-band IIP 3 of -0.35 dBm. The performance meets Bluetooth Low-Energy requirements and is competitive with other sub-mW receivers.

A highly linear Trans-Impedance Amplifier (TIA) for 5G New Radio mobile communication receivers is presented. The TIA has a cut-off frequency programmable from 500 MHz up to 1.5 GHz. The TIA is based on a Feed-Forward compensated amplifier. To ensure stability while achieving high bandwidth and low power, an inductor is used inside the feed-forward stage. A test chip has been realized in 28 nm CMOS technology. The TIA achieves an In-band OIP3 of 32.9 dBm and the output integrated noise from 20 MHz to 1.5 GHz is lower than 300 µ V rms with a power dissipation of 17 mW.

This article presents a 2-GS/s time-interleaved (TI) 10-bit capacitive digital-to-analog converter (CDAC) for self-interference-cancellation (SIC) application. It is also capable of working as a non-TI & stand-alone CDAC with 1-GS/S clock frequency. By taking advantage low parasitic capacitance and equivalent parasitic capacitance at bottom and top plate of MIM capacitor, the split-capacitor t...

An ultralow power (ULP) low-noise receiver front-end for the BLE application is presented in this letter. The tradeoff between noise and power consumption is mitigated by employing a transformer-based passive gm-boosting common-gate low noise transconductance amplifier (LNTA). Local-positive feedback (LPF) and feedforward (FF) noise cancellation techniques are combined in the LNTA to further lower noise. After the passive mixer, a TIA implements complex filtering with a moderate conversion gain. The receiver front-end, fabricated in TSMC 28-nm process, consumes only 440 mu Wunder 0.9-V supply with a minimum noise figure of 4.8 dB.

An open-loop baseband filter with bandwidth of 1GHz suitable for a receiver operated in the 5G high frequency band (above 24GHz) is presented. The filter is based on a gain boosted Common Gate topology that implements a 2 nd order low-pass filter in the current domain. A frequency-dependent active negative capacitance circuit is used to boost the quality factor of the filter. This not only improves in-band flatness but also increases out-of-band selectivity. A test chip has been realized in 28nm CMOS technology. The filter bandwidth can be programmed from 650 MHz to 1 GHz and the current gain changed by 14 dB, with the power dissipation scaling from 11 mW to 5 mW. In-band IIP3 is +2 dBm and the input noise integrated from 10 MHz to 1 GHz is lower than 170 μV rms .

This letter proposes an ultralow-power mixer-first front-end using voltage-mode boosting. The voltage gain is achieved passively by using capacitive stacking. By employing N-path filtering technique, this front-end achieves high out-of-band (OOB) rejection which results in high in/OOB linearity. A prototype, composed of four-paths with six stages of switched capacitors, is fabricated in 28-nm CMOS technology, and achieves 29-dB gain, 5.7-dB noise figure (NF) and +10-dBm OOB-IIP3 while consuming less than 140 mu W.

A modified noise/nonlinearity cancellation low-noise transconductance amplifier (LNTA) based on an inductively degenerated common-source stage is proposed to improve linearity. The linearity of the proposed LNTA is analyzed using the Volterra series yielding closed-form equations for the third-order input intercept point (IIP3) that shows excellent matching with the simulation results. The derived equations for noise figure (NF) and IIP3 are simple enough to be used for design optimization. Calculations and simulation results show that the proposed LNTA is more linear than a conventional one, while NF approximately remains unchanged. Another feature of the proposed noise-canceling LNTA is that no additional baseband recombination stage is needed, leading to reduced complexity in the receiver baseband stage. The NF and out-of-band (OOB) IIP3 of the receiver is about 3.3 dB and more than 20 dBm, respectively. The receiver consumes 10.5 mA from 1.8-V supply voltage. The current consumption of the LO divider is 6.5 mA from a dedicated 1-V supply voltage.

This letter shows a fully differential linear transimpedance amplifier designed for the emerging coherent optical communications for high data rate transmissions. The purpose of this letter is to present a possible solution in 28-nm CMOS technology instead of the most frequently used BiCMOS. The idea is to take advantage of the linearity of CMOS to partially offset its inherently lower transconductance over current ratio, which typically limits the bandwidth. The proposed TIA presents a -3-dB bandwidth equal to 42 GHz and its transimpedance gain can be programmable from 78 to 36 dBΩ with four variable gain stages. At maximum gain, the measured average input noise is equal to 18 pA√Hz whereas the maximum total harmonic distortion for an output voltage swing of 500-mV peak-to-peak differential is always lower than 1.8% over the entire gain range. The complete transimpedance amplifier including the bias and dc offset cancellation circuits consumes 319 mW from a 2.4-V supply voltage.

The design of a mixer-first wideband receiver with RF bandwidth of 260 MHz suitable for 5G applications below 6 GHz is presented. The transimpedance amplifier immediately following the passive mixer is based on a low-power modified regulated cascode with enhanced selectivity, instead of a conventional shunt-feedback architecture. At the mixer output, thanks to a positive feedback capacitance multiplication, a third-order low-pass filtering in the current domain is performed. A simplified non-linear model is used to demonstrate that, thanks to the improved selectivity, linearity close to the band edge is highly improved. Wide bandwidth, high linearity, and low power are thus achieved. Measurements on a 28-nm CMOS chip prototype show alternate channel IIP3, IIP2, and P1 dB of +22, +70, and +3 dBm, respectively. Receiver (RX) noise figure (NF) is 5.5 dB, while power consumption is 21.6 mW (in the signal path) and 7.8 mW/GHz (for local oscillator (LO) generation) with 1.8-/1.2-V supply.