ABSTRACT The Internet of Things (IoT) has caused an exponential increase in the number of connected devices. This brings the Internet closer to everyday activities and enables data collection that can be used to create and improve a great variety of services. However, more powerful storage and processing capabilities are required to service all these devices. Modelling and Simulation (M&S) can help to deploy IoT infrastructure, providing flexible and powerful mechanisms to study and compare different strategies. In this scenario, Micro Data Centers (MDCs) are an effective solution to reduce overwhelmed Cloud Data Center infrastructures. This paper explores an M&S methodology to study the overall power consumption of a healthcare IoT scenario, where patients wear non-intrusive monitoring devices that periodically generate computing tasks. We extract the layout of existing urban infrastructures, simulate the monitored population’s behaviour, and compare the power consumption of several data centre configurations.

The natural progression from classic Model-Based Systems Engineering (MBSE) methodologies to Modeling and Simulation-Based Systems Engineering (M&SBSE) brings the need for more flexible and powerful validation tools. Completing the structure and descriptions of static models with self-diagnosis greatly facilitates the development, implementation, and validation of complex models. However, current simulation development environments and libraries often lack providing complete tools to validate these complex models straightforwardly and with the proper level of detail. In this article, we tackle this issue transferring one of the traditional software testing methods, unit testing, to the modeling and simulation field. To this end, we integrate a unit-testing method to the DEVS methodology, allowing the specification of expected states, outcomes, and behaviors of the simulation modules in an XML-based syntax, in all the levels of the hierarchical design. As a result, this methodology enables the generation of powerful and easy-readable verification files.

Several models in the literature correlate blood pressure (BP) with the electrocardiogram (ECG) and photoplethysmogram (PPG) signals. These studies show substantial differences and have not been adequately compared. The MIMIC database, containing intrusive BP measures collected in a hospital setting, has been used to perform an extensive study of different models and variables extracted from the PPG and ECG signals. The best BP estimator model obtained is alpha/PAT(2) + beta HR + delta, where PAT is the Pulse Arrival Time and HR is the heart rate. This model allows the monitoring of fast BP trends and fluctuations. If absolute values of BP were required, the model would have to be calibrated with real BP measures. The model, with periodic recalibrations, meets the Association for the Advancement of Medical Instrumentation (AAMI) requirements for diastolic BP but not for systolic BP, for which the mean error is close to 8 mmHg. (c) 2020 Elsevier Ltd. All rights reserved.

Chronic diseasesChronic diseases represent the major health problems of the twenty-first century. These diseases kill 41 million people each year, equivalent to 71% of all deaths globally. The major chronic diseasesChronic diseases listed by the World Health Organization are cardiovascular diseases, cancer, chronic respiratory diseases, diabetes mellitus, and neurodegenerative disorders. Monitoring and maintaining normal values for key healthMigraine metrics play a primary role in reducing chronic disease risk. Powerful mechanisms based on prevention to combat the chronic disease crises are currently present and continue to evolve. A new healthcareHealthcare delivery model is needed to implement these mechanisms effectively. This model implies the utilization of wearable devices connected to the Cloud, allowing continuous monitoring and prevention of chronic disease crises. Standard Modeling and Simulation (M&S) methodologies created to design Cyber-Physical Systems (CPS)Cyber-physical system design and deploy them into the Cloud can help design and implementPhysical implementation complex scenarios. In this chapter, we show the automatic CPS implementation process of a robust migraineMigraine prediction systemPrediction system that allows the generation of alarms before the appearance of new pain episodes. This method is used to implement the device in an FPGA and to study the scalability of the proposed infrastructure, the integration of the designed device into an Internet of Things (IoT) ecosystem is demonstrated.

Several of the major causes of death in the world are related to neurological diseases, like strokes, sclerosis, or Parkinson's. As a consequence, extraordinary amounts of clinical information are collected. With proper Modeling and Simulation (MS) techniques, predictive models can be defined to help physicians in their diagnoses. We have come to the conclusion that the implementation of an abstract MS methodology to facilitate the processing and modeling of the collected data would be of great help. In this paper, we focus on the development of such an abstract framework, mainly aimed at facilitating and automating the process of data collection and predictive and diagnose models. As a use case, we show how this methodology is applied to determine the stroke type and exitus (i.e. probability of death) of stroke patients in the early stages of their episodes. The best models are evaluated and constantly updated to generate these predictions.

In this paper, an alternative to the traditional methodology related to signal processing-like subjects is proposed. These are subjects that require a deep mathematical and theoretical basis, but the practical goal is not often emphasized, which drives students to lose interest in the subject. Thus, a software-defined radio environment is proposed to provide a more practical view of the subject. This solution consists of an open hardware–software platform able to capture and process a wide range of frequencies. HackRF is the hardware component, while GNU Radio will provide the graphical support to this device. The tests performed with a set of 36 students have revealed that they are more satisfied with this framework than just employing a traditional equation-based environment as Matlab. Furthermore, their scores in the exams also support the suitability of the proposed platform.

This paper proposes energy-efficient approximate multipliers based on the Mitchell's log multiplication, optimized for performing inferences on convolutional neural networks (CNN). Various design techniques are applied to the log multiplier, including a fully-parallel LOD, efficient shift amount calculation, and exact zero computation. Additionally, the truncation of the operands is studied to create the customizable log multiplier that further reduces energy consumption. The paper also proposes using the one's complements to handle negative numbers, as an approximation of the two's complements that had been used in the prior works. The viability of the proposed designs is supported by the detailed formal analysis as well as the experimental results on CNNs. The experiments also provide insights into the effect of approximate multiplication in CNNs, identifying the importance of minimizing the range of error. The proposed customizable design at w = 8 saves up to 88 percent energy compared to the exact fixed-point multiplier at 32 bits with just a performance degradation of 0.2 percent for the ImageNet ILSVRC2012 dataset.

While partial carry-save adders are easily designed by splitting them into several fragments working in parallel, the design of partial carry-save multipliers is more challenging. Prior approaches have proposed several solutions based on the radix-4 Booth recoding. This technique makes it possible to diminish the height of a multiplier by half, this being the most widespread option when designing multipliers, as only easy multiples are required. Larger radices provide further reductions at the expense of the appearance of hard multiples. Such is the case of radix-8 Booth multipliers, whose critical path is located at the generation of the $3X$ multiple. In order to mitigate this delay, in our prior works, we proposed to first decouple the $3X$ computation and introduce it in the dataflow graph, leveraging the available slack. Considering this, we then present a partial carry-save radix-8 Booth multiplier that receives three inputs in this format, namely, the multiplicand, the multiplier, and the $3X$ multiple. Moreover, the rest of the datapath is adapted to work in partial carry-save. In comparison with conventional radix-4 and radix-8 Booth-based datapaths, the proposal is able to diminish the execution time and energy consumption while benefits from the area reduction provided by the selection of radix 8. Furthermore, it outperforms prior state-of-the-art partial carry-save multipliers based on radix 4.

This work presents a new modular and low-complexity algorithm for the delineation of the different ECG waves (QRS, P and T peaks, onsets, and end). Involving a reduced number of operations per second and having a small memory footprint, this algorithm is intended to perform real-time delineation on resource-constrained embedded systems. The modular design allows the algorithm to automatically adjust the delineation quality in runtime to a wide range of modes and sampling rates, from a ultralow-power mode when no arrhythmia is detected, in which the ECG is sampled at low frequency, to a complete high-accuracy delineation mode, in which the ECG is sampled at high frequency and all the ECG fiducial points are detected, in the case of arrhythmia. The delineation algorithm has been adjusted using the QT database, providing very high sensitivity and positive predictivity, and validated with the MIT database. The errors in the delineation of all the fiducial points are below the tolerances given by the Common Standards for Electrocardiography Committee in the high-accuracy mode, except for the P wave onset, for which the algorithm is above the agreed tolerances by only a fraction of the sample duration. The computational load for the ultralow-power 8-MHz TI MSP430 series microcontroller ranges from 0.2% to 8.5% according to the mode used.

In 1951 A. Booth published his algorithm to efficiently multiply signed numbers. Since the appearance of such algorithm, it has been widely accepted that radix 4-based Booth multipliers are the most efficient. They allow the height of the multiplier to be halved, at the expense of a simple recoding that consists of just shifts and negations. Theoretically, higher radix should produce even larger reductions, especially in terms of area and power, but the recoding process is much more complex. Notably, in the case of radix 8 it is necessary to compute 3X, X being the multiplicand. In order to avoid the penalty due to this calculation, we propose decoupling it from the product and considering 3X as an extra operation within the application's Dataflow Graph (DFG). Experiments show that typically there is enough slack in the DFGs to do this without degrading the performance of the circuit, which permits the efficient deployment of radix 8 multipliers that do not calculate the 3X multiple. Results show that our approach is 10% and 17% faster than radix 4 and radix 8 Booth based implementations, respectively, and 12% and 10% more energy efficient in terms of Energy Delay Product.

High Efficiency Video Coding (HEVC) is the current encoding standard, and achieves greater compression efficiency than the previous ones. The main objective of HEVC consists in retaining the same quality while employing less than 50% of the bitstream size when compared with the previous H.264 standard. This has, however, been achieved by considerably increasing the complexity of the algorithm. In this article, we exploit certain regions with homogeneous texture, also known as smooth regions, which do not require complex processing. Hence, an HEVC flow based on this spatial homogeneity classification is proposed to accelerate the encoding process. For this purpose, several fast intra and inter prediction methods are presented. Furthermore, a subjective quality improvement of the entire video sequence is proposed. When compared with the reference HM16.2 test model, our experiments show that it is possible to reduce the encoding time by up to 77.9% with negligible quality loss and a maximum bitrate increase of 0.5%. When considering the common test conditions suggested by JCT-VT, the average BD-Rate increase is 0.58%, 0.87% and 1.02%, with an encoding time reduction of 40.5%, 25.3% and 25.4 for all intra, low-delay P and random access configurations, respectively.

The discrete event system specification formalism, which supports hierarchical and modular model composition, has been widely used to understand, analyze and develop a variety of systems. Discrete event system specification has been implemented in various languages and platforms over the years. The DEVStone benchmark was conceived to generate a set of models with varied structure and behavior, and to automate the evaluation of the performance of discrete event system specification-based simulators. However, DEVStone is still in a preliminary phase and more model analysis is required. In this paper, we revisit DEVStone introducing new equations to compute the number of events triggered. We also introduce a new benchmark with a similar central processing unit and memory requirements to the most complex benchmark in DEVStone, but with an easier implementation and with it being more manageable analytically. Finally, we compare both the performance and memory footprint of five different discrete event system specification simulators in two different hardware platforms.

Functional Units that are designed to receive inputs and produce outputs using a non-redundant format typically exhibit an inferior performance. In order to overcome this limitation, the carry-save and partial carry-save formats have been proposed. Both approaches are very suitable when implementing addition trees. Nevertheless, if there are multiplications in the datapath, the inputs to the multiplier must be reduced to a non-redundant form, to avoid applying the distributive property. In this paper we present a multiplier able to receive two numbers in partial carry-save format, and produce a result in partial carry-save format as well. This is done by modifying the Booth encoder and leveraging the generate and propagate group signals that are available because of the partial carry-save format. Hence, this can allow to fully implement datapaths without additional penalty cycles due to reductions to non-redundant forms. Experiments show that our proposed multiplier has 15 percent shorter delay with respect to a conventional Booth radix-4 multiplier. Moreover, when combining it with partial carry-save adders it is possible to reduce 36 percent execution time on average for several benchmarks, achieving a 32.7 percent reduction in the Energy Delay Product at the same time.

Due to the necessity of handling unexpected events in execution time, e.g., to support process variations, new mechanisms for dealing with every possible behavior of the datapath must be developed. Conventional centralized controllers can only handle very few dynamic events. Distributed controllers, on the other hand, are able to support every combination of events. These controllers are composed of several finite state machines, which are interconnected via a global coordinator. The use of this type of controller obliges to check the hazards between operations in run time, which entails some penalty in the controller complexity. In this paper, a new methodology for deploying a distributed controller over a set of clusters is presented. A register binding algorithm specially suited for distributed controllers has also been developed. It combines a clustering method and a least recently used policy to reduce the number of hazards in run time. Furthermore, our methodology allows the exploration of different solutions by tuning the input parameters of the binding algorithm. Several studies evaluating the execution time and area tradeoffs are presented to support our techniques. Results show that for some cases it is possible to reduce more than 50% the expected execution time, at the expense of a slight area increase.

Data Centers are huge power consumers, both because of the energy required for computation and the cooling needed to keep servers below thermal redlining. The most common technique to minimize cooling costs is increasing data room temperature. However, to avoid reliability issues, and to enhance energy efficiency, there is a need to predict the temperature attained by servers under variable cooling setups. Due to the complex thermal dynamics of data rooms, accurate runtime data center temperature prediction has remained as an important challenge. By using Grammatical Evolution techniques, this paper presents a methodology for the generation of temperature models for data centers and the runtime prediction of CPU and inlet temperature under variable cooling setups. As opposed to time costly Computational Fluid Dynamics techniques, our models do not need specific knowledge about the problem, can be used in arbitrary data centers, re-trained if conditions change and have negligible overhead during runtime prediction. Our models have been trained and tested by using traces from real Data Center scenarios. Our results show how we can fully predict the temperature of the servers in a data rooms, with prediction errors below 2 degrees C and 0.5 degrees C in CPU and server inlet temperature respectively. (C) 2016 Elsevier B.V. All rights reserved.

The IEEE-802.15.4 standard is poised to become the global standard for low data rate, low energy consumption Wireless Sensor Networks. By assigning the same sets of contention access parameters for all data frames and nodes, the Contention Access Period (CAP) of the slotted IEEE-802.15.4 currently provides an even channel access functionality and no service differentiation. However, some applications may require service differentiation and traffic prioritization support to accommodate high-priority traffic (e.g., alarms). In order to simulate a scenario in which different sets of access parameters for different node classes can be configured, this paper develops a Markov-chain-based model of the CAP of the IEEE-802.15.4-MAC. Our Markov model can be used to evaluate the impact of mixing node classes in important factors like the throughput, energy consumption, probability of delivery and the packet latency. The model has been used to provide traffic differentiation in a high saturation scenario in which a set of nodes can be configured to increase 76% the probability of sending a packet and reduce 58% latency, with a 69% energy penalty, in comparison with a standard scenario. The accuracy of the Markov model is validated by extensive ns-2 simulations.

Currently, the most powerful supercomputers can provide tens of petaflops. Future many-core systems are estimated to provide an exaflop. However, the power budget limitation makes these machines still unfeasible and unaffordable. Floating Point Units (FPUs) are critical from both the power consumption and performance points of view of today's microprocessors and supercomputers. Literature offers very different designs. Some of them are focused on increasing performance no matter the penalty, and others on decreasing power at the expense of lower performance. In this article, we propose a novel approach for reducing the power of the FPU without degrading the rest of parameters. Concretely, this power reduction is also accompanied by an area reduction and a performance improvement. Hence, an overall energy gain will be produced. According to our experiments, our proposed unit consumes 17.5%, 23% and 16.5% less energy for single, double and quadruple precision, with an additional 15%, 21.5% and 14.5% delay reduction, respectively. Furthermore, area is also diminished by 4%, 4.5 and 5%.

The recent introduction of Variable Latency Functional Units (VLFUs) has broadened the design space of High-Level Synthesis (HLS). Nevertheless their use is restricted to only few operators in the datapaths because the number of cases to control grows exponentially. In this work an instance of VLFUs is described, and based on its structure, the average latency of tree structures is improved. Multispeculative Functional Units (MSFUs) are arithmetic Functional Units that operate using several predictors for the carry signal. In spite of utilizing more than a predictor, none or only one additional very short cycle is enough for producing the correct result in the majority of the cases. In this paper our proposal takes advantage of multispeculation in order to increase the performance of tree structures with a negligible area penalty. By judiciously introducing these structures into computation trees, it will only be necessary to predict the carry signals in certain selected nodes, thus minimizing the total number of predictions and the number of operations that can potentially mispredict. Hence, the average latency will be diminished and thus performance will be increased. Our experiments show that it is possible to improve 26% execution time. Furthermore, our flow outperforms previous approaches with Speculative FUs.

Variable Latency Adders are attracting strong interest for increasing performance at a low cost. However, most of the literature is focused on achieving a good area-delay tradeoff. In this paper we consider multispeculation as an alternative for designing adders with low energy consumption, while offering better performance than the corresponding non-speculative ones. Instead of introducing more logic to accelerate the computation, the adder is split into several fragments which operate in parallel, and whose carry-in signals are provided by predictor units. On the one hand, the critical path of the module is shortened, and on the other hand the frequent useless glitches produced in the carry propagation structure are diminished. Hence, this will be translated into an overall energy reduction. Several experiments have been performed with linear and logarithmic adders, and results show energy savings by up to 90% and 70%, respectively, while achieving an additional execution time decrease. Furthermore, when utilized in whole datapaths with current control techniques, it is possible to reduce execution time by 24.5% (34% best case) and energy by 32% (48% best case) on average.

Leakage power consumption is a com- ponent of the total power consumption in data cen- ters that is not traditionally considered in the set- point temperature of the room. However, the effect of this power component, increased with temperature, can determine the savings associated with the careful management of the cooling system, as well as the re- liability of the system. The work presented in this paper detects the need of addressing leakage power in order to achieve substantial savings in the energy consumption of servers. In particular, our work shows that, by a careful detection and management of two working regions (low and high impact of thermal- dependent leakage), energy consumption of the data- center can be optimized by a reduction of the cooling budget.