Circuit simulation may be used to verify ESD robustness prior to tape-out, but the accuracy of a high-current ESD simulation is often limited by the foundry PDK MOSFET model. This work presents a scalable MOSFET wrapper for ESD simulations that augments a PDK model to provide an accurate representation of the transistor's high current response while preserving the accuracy of the PDK model in simulations of normal circuit operation. The wrapper is intended for post-layout simulation; the wrapper is scalable with respect to layout parameters and integrates directly into a back-end extracted netlist. Three different implementations of the model are presented, allowing the user to make trade-offs between accuracy, complexity, and scalability.

AI tools used for chip design and manufacturing are moving from prediction to generation. This survey examines generative AI tools across the full silicon lifecycle. It covers analog/mixed-signal, logic and physical design, and manufacturing with yield and reliability. We organize recent work by what is generated—circuits, scripts, layouts, masks, and surrogates—and by how generation is grounded through retrieval, simulators, and physics. We give a clear taxonomy.We highlight emerging cross-stage dependencies linking early design choices to downstream manufacturability, and we identify where the literature has not yet closed those loops. We synthesize qualitative considerations for choosing retrieval-grounded LLM agents, task-specific generators, and physics-aware surrogates, while noting that controlled head-to-head evidence remains limited. We aim this work to be a broad entry point for researchers and practitioners who need a clear map and practical guidance on generative methods across the silicon lifecycle.

This work presents a comprehensive design methodology for temperature-dependent yield analysis of UCIe-A die-to-die interconnects on silicon interposers. Surrogate models are developed to enable rapid design-space exploration while capturing the effects of process variations on system-in-package design parameters. These models allow identification of inter-poser designs that satisfy channel-loss and crosstalk specifications while maximizing yield at the target channel temperature. As a demonstration, yield-optimal designs are identified for both ×32 and ×64 UCIe interfaces. The same temperature-aware methodology is extended to UCIe 3.0 channel specifications supporting data rates up to 64 GT/s. The surrogate models are benchmarked against full-wave electromagnetic simulations, demonstrating close agreement across the explored design space. To validate the physical fidelity of the EM simulations, a representative ×32 channel is fabricated and characterized. De-embedded insertion-loss measurements exhibit excellent agreement with the EM simulations, with a maximum deviation of less than 0.2 dB at 16 GHz for 1-mm and 2-mm interconnects with 2.4/2 μm line/spacing. The combined agreement among surrogate predictions, EM simulations, and measurements confirms the accuracy and reliability of the overall modeling approach.

This work presents a methodology for generating temperature-dependent channel models for die-to-die interfaces. The parameterized models are represented as distributed RLGC networks. The modeling methodology is demonstrated for x32 and x64 UCIe interfaces implemented on a silicon interposer, achieving average accuracy greater than 99% when predicting channel loss and crosstalk. These surrogate models are over five orders of magnitude faster than a single electromagnetic simulation, significantly expediting design space exploration.

Today, industry pioneers dream of developing general-purpose AI engineers capable of designing and building humanity's most ambitious projects–from starships that will carry us to distant worlds to Dyson spheres that harness stellar energy. Yet engineering design represents a fundamentally different challenge for large language models (LLMs) compared to traditional textbook-style problem solving or factual question answering. Real-world engineering design demands the synthesis of domain knowledge, navigation of complex trade-offs, and management of the tedious processes that consume much of practicing engineers' time. Despite these shared challenges across engineering disciplines, no benchmark currently captures the unique demands of engineering design work. In this work, we introduce ENGDESIGN, an Engineering Design benchmark that evaluates LLMs' abilities to perform practical design tasks across nine engineering domains: Operating System Design, Computer Architecture Design, Control System Design, Mechanical Systems, Structural Design, Digital Hardware Design, Analog Integrated Circuit Design, Robotics, and Signal Processing. Unlike existing benchmarks that focus on factual recall or question answering, ENGDESIGN uniquely emphasizes LLMs' ability to synthesize domain knowledge, reason under constraints, and generate functional, objective-oriented designs. Each task in ENGDESIGN represents a real-world engineering design problem, accompanied by a detailed task description specifying design goals, constraints, and performance requirements. We pioneer a simulation-based evaluation paradigm where LLM-generated designs undergo rigorous testing through executable, domain-specific simulations-from circuit SPICE simulations to structural finite element analysis, from control system validation to robotic motion planning.

As the end of Moore's law approaches, chiplet integration technology (or chiplet technology) has emerged to revolutionize future semiconductor chip design. Chiplet technology provides unique advantages over 3-D-stacking technology, including a more cost-efficient and thermal-friendly integration of heterogeneous technologies. Although chiplet technologies have already begun to be used by the latest commercial chips, they have not been explored for commodity dynamic random access memory (DRAM) design yet. Harnessing its advantages for DRAM for the first time, this article evaluates the feasibility of chiplet-based DRAM architecture, considering various physical and electrical constraints imposed by a standard chiplet interface i.e., universal chiplet interconnect express (UCIe). We further explore the DIMM architectures that simplify module packaging and assembly, leading to reductions in total die size and overall costs. The comprehensive cross-level analysis (i.e., device, circuit, chip, and system levels) shows that chiplet-based DRAM reduces t_RCD + t_CAS, latency-critical DRAM timing parameters, by 1.32x-1.39x, at the same energy consumption. In addition, a 1.39x-2.28x improvement in t_RRD is obtained. The reduced DRAM timing parameters improve the overall system performance by up to 8.8%-24.7% (geomean 3.4%-8.4%) in real-life benchmarks. The chiplet-based heterogeneous integration achieves a 1.27x higher chip-level yield compared with the monolithic chip, along with up to 10% reduction in overall cost compared with traditional DIMMs at emerging process technologies.

This work presents on-chip pulse generators fabricated in 16-nm and 65-nm CMOS technologies and used to measure the breakdown voltage of high-k and SiO2 gate dielectrics on a sub-nanosecond timescale. The pulse generators produce clean single-shot pulses with amplitude up to 7.5 V and pulse width as short as 100 ps. The sub-ns applicability of established models for TDDB voltage acceleration and area scaling is assessed using the pulse generator.

This work presents an ESD solution for high-speed serial IO pins, in which a STI-poly-bounded silicon-controlled rectifier (SCR) is integrated into an impedance matching circuit. The proposed all-pass secondary protection network provides excellent voltage clamping under CDM-like conditions, resulting in a peak voltage of just 2 V in response to 5-A 1-ns VFTLP current injection. Integrated with a T-coil circuit, the network achieves a bandwidth above 40 GHz, as well as broadband impedance matching.

An on-chip active probe that enables measurement of ESD transients at internal circuit nodes is demonstrated. The probe’s bandpass characteristics are targeted for CDM. The probe is used to capture transient voltage waveforms at internal nodes of four high-speed transmitters located on a packaged IC during VF-TLP testing.

This work introduces a new loss function for modeling dielectric lifetime distributions with thickness nonuniformity. It is applicable to both maximum likelihood estimation and to a previously introduced machine learning (ML) framework, providing better agreement between measurement data and generated distributions. The ML method is used to model die and wafer level lifetime distributions and thickness variation. An analytic expression relating dielectric thickness to leakage current or vice versa can be extracted.

This work presents an on-chip ESD protection architecture for high-speed automotive SerDes receivers. The ESD protection, composed of primary, secondary and auxiliary clamps, is designed to withstand system-level ESD stress. The primary protection is provided by a bidirectional SCR that can sink 15 A of 100-ns TLP current. Impedance matching and bandwidth extension are achieved by integrating the ESD protection with a T-coil circuit.

Technology scaling and increased data rates make it near impossible to achieve historic levels of electrostatic discharge (ESD) robustness. This heightens the need for pre-Si verification that a design's ESD level is above a critical value, below which the yield loss and the number of field returns are expected to be high. Transient simulation plays a role in ESD design verification and requires the availability of accurate compact models of the various semiconductor devices, which lie along the discharge path. The compact models included in a foundry process design kit (PDK) are not accurate at ESD current levels. This article describes compact models that have been developed in the ESD device research community. It reviews the measurements used to characterize ESD protection devices and acquire data for model parameter extraction. It is concluded that obtaining accurate measurement data is challenging and this impedes the widescale adoption of ESD compact models.

This work demonstrates a Verilog-A model that may be interconnected to a PDK MOSFET model; the composite model is valid at ESD current levels while retaining the accuracy of the PDK model for ac, dc, and transient simulation at current levels reflective of normal operating conditions. The model’s accuracy under ESD conditions is verified by comparing simulation results to TLP and VF-TLP measurement data.

This work presents an interposer design methodology for UCIe die-to-die interfaces that maximizes yield given a set of signal integrity specifications. Four different routing configurations on a silicon interposer are considered, and the cost, performance, and yield tradeoffs are elucidated. The fabrication steps for the D2D interconnects are outlined and sources of yield-limiting variability are identified. The yield analysis is expedited by the use of a Gaussian Process Regression surrogate model.

This work presents an active feedback-based high voltage tolerant (5 V) supply clamp for ESD protection in 16-nm FinFET CMOS technology. The proposed trigger circuit biases the BigFETs for maximum ESD robustness and employs positive feedback to maintain the clamp in the on-state such that the clamp can shunt the ESD current for the duration of an HBM event. Negative feedback circuitry is employed to turn the clamp off in case of mistriggering. The clamp is shown to be capable of discharging up to 4-kV HBM current.

During charged device model (CDM) electrostatic discharge (ESD) events, MOSFET gate oxides may be exposed to high voltage stress lasting for a few hundred picoseconds or less, and the gate oxide breakdown voltage is an important parameter for ESD designers. This work presents an on-chip pulse generator fabricated in a 65-nm CMOS process capable of producing clean single-shot pulses with amplitude up to 6 V and pulse width as short as 200 ps. The pulse generator is used for an experimental investigation of MOS gate oxide breakdown voltage on a sub-ns timescale and to assess the validity of the power-law model.

This work presents a compact model for N-Well ESD diodes, including the parasitic PNP. A schematic representation of the model is similar to the SPICE Gummel-Poon model, but the implementation differs. The proposed model uses a non-quasi-static description of the stored charge, which facilitates accurate simulation of the diode’s transient response to ESD. The very high-level injection which occurs during ESD is modeled in a manner suitable for the parasitic PNP with its relatively large base width.

PNP bipolar transistors are an ESD protection solution for high-voltage analog products. Using both measurements and TCAD simulations, this work analyzes the effects of the deep collector P-Well implants on the I-V characteristic of a high-voltage lateral PNP. Design guidelines for a PNP protection device are formulated; specifically, it is recommended to use a deep and narrow collector and minimize vertical non-uniformity in the doping profile.

This work advances the current understanding and performance assessment of chiplet interfaces by providing a framework for modeling and joint simulation of signal and power integrity of BoW-based die-to-die interconnects with advanced packaging technology. The study covers data rates up to 16 Gbps. This paper presents a circuit-level implementation of the BoW slice that consists of a driver on one chiplet and a receiver on another chiplet. This work compares the performance of various combinations of high-density transmission lines with different line-and-space and wirelengths. It presents configurations of the BoW data lines that have extremely low power dissipation, less than 0.2 pJ/bit at 8 and 16 Gbps.

The effect of temperature on the reliability and performance of electrical components and integrated circuits warrants the inclusion of thermal considerations in the early stages of electronic system design. However, the many design parameters involved in the design of the package and the die or macro placement, along with the use of expensive thermal simulations, poses difficulty for conventional optimization algorithms. To overcome that hurdle, this work proposes an efficient Bayesian optimization algorithm which is demonstrated for two early-stage design problems. First, the proposed algorithm is used for the thermal-aware placement of macros with a variable aspect ratio. Second, the proposed Bayesian optimization algorithm is utilized in a two-stage process to optimize the die placement and the package design parameters of a multi-chip module.