Electrical contacts to atomically thin 2-D semiconductors are considered as the hindering aspect of electronic devices based on these materials. The high resistance of such contacts stems from their Schottky nature in contrast to the desired low-resistance Ohmic contacts. This issue of Schottky contacts is thus one of the major inhibitors to the integration of 2-D materials into mainstream technology. In this work, we explore contact resistance ( ${R}_{\text {C}}$ ) to atomically thin 2-D semiconductors in terms of the injected current through the Schottky barrier (SB) by using the Landauer-Büttiker formalism as well as experimental measurements and technology computer aided design (TCAD) simulations. We show that the SB height and width, which are determined by the metal–semiconductor interface and the number of charge carriers in the semiconductor channel, respectively, affect ${R}_{\text {C}}$ when it is relatively high ( ${R}_{\text {C}} >$ 1 $\text{k}\Omega \cdot \mu \text{m}$ ). However, the number of transport modes for carrier injection is the limiting factor for aggressive ${R}_{\text {C}}$ lowering ( ${R}_{\text {C}} < $ 1 $\text{k}\Omega \cdot \mu \text{m}$ ), even for near-zero SB height. Our results show that to reduce ${R}_{\text {C}}$ below $100~\Omega \cdot \mu \text{m}$ , large number of transport modes are required, which can be accomplished through raising the number of channel carriers above 5. 1013 cm-2 by means of heavy doping or gating. Our conclusions offer insight for future contact engineering and can explain recently published state-of-the-art results.

Achieving good electrical contacts is one of the major challenges in realizing devices based on atomically thin 2D semiconductors. Several studies have examined this hurdle, but a universal understanding of the contact resistance (Rc) and an underlying approach to its reduction are currently lacking. Here, the classical Rc transmission line model description of contacts to 2D materials is experimentally examined, and a modification based on an additional lateral resistance component, namely, the junction resistance (Rjun) is offered. A combination of transfer length method and contact‐end measurements to characterize contacts to monolayer MoS2 and separate the different Rc components is used. Technology computer‐aided design simulations are also used to study Rc in Fermi‐level pinned and unpinned contacts. This study finds that Rjun is the dominating component of Rc in atomically thin semiconductor devices, and is also responsible for most of the back‐gate bias and temperature dependence. The experimental results help understand the underlying physics of state‐of‐the‐art contact engineering in the context of minimizing Rjun.

Real-time thermal sensing on flexible substrates could enable a plethora of new applications. However, achieving fast, sub-millisecond response times even in a single sensor is difficult, due to the thermal mass of the sensor and encapsulation. Here, we fabricate flexible monolayer molybdenum disulfide (MoS2) temperature sensors and arrays, which can detect temperature changes within a few microseconds, over 100× faster than flexible thin-film metal sensors. Thermal simulations indicate the sensors' response time is only limited by the MoS2 interfaces and encapsulation. The sensors also have high temperature coefficient of resistance, ∼1-2%/K and stable operation upon cycling and long-term measurement when they are encapsulated with alumina. These results, together with their biocompatibility, make these devices excellent candidates for biomedical sensor arrays and many other Internet of Things applications.

Strain engineering is an important method for tuning the properties of semiconductors and has been used to improve the mobility of silicon transistors for several decades. Recently, theoretical studies have predicted that strain can also improve the mobility of two-dimensional (2D) semiconductors, e.g., by reducing intervalley scattering or lowering effective masses. Here, we experimentally show strain-enhanced electron mobility in monolayer MoS2 transistors with uniaxial tensile strain, on flexible substrates. The on-state current and mobility are nearly doubled with tensile strain up to 0.7%, and devices return to their initial state after release of the strain. We also show a gate-voltage-dependent gauge factor up to 200 for monolayer MoS2, which is higher than previous values reported for sub-1 nm thin piezoresistive films. These results demonstrate the importance of strain engineering 2D semiconductors for performance enhancements in integrated circuits, or for applications such as flexible strain sensors.

Two-dimensional (2D) semiconducting transition metal dichalcogenides could be used to build high-performance flexible electronics. However, flexible field-effect transistors (FETs) based on such materials are typically fabricated with channel lengths on the micrometre scale, not benefitting from the short-channel advantages of 2D materials. Here, we report flexible nanoscale FETs based on 2D semiconductors; these are fabricated by transferring chemical-vapour-deposited transition metal dichalcogenides from rigid growth substrates together with nano-patterned metal contacts, using a polyimide film, which becomes the flexible substrate after release. Transistors based on monolayer molybdenum disulfide (MoS2) are created with channel lengths down to 60 nm and on-state currents up to 470 μA μm−1 at a drain–source voltage of 1 V, which is comparable to the performance of flexible graphene and crystalline silicon FETs. Despite the low thermal conductivity of the flexible substrate, we find that heat spreading through the metal gate and contacts is essential to reach such high current densities. We also show that the approach can be used to create flexible FETs based on molybdenum diselenide (MoSe2) and tungsten diselenide (WSe2). By transferring two-dimensional semiconductors from rigid growth substrates together with nano-patterned metal contacts, flexible field-effect transistors can be fabricated with channel lengths down to 60 nm.

Achieving good electrical contacts is one of the major challenges in realizing devices based on atomically thin two-dimensional (2D) semiconductors. Several studies have examined this hurdle, but a universal understanding of the contact resistance and an underlying approach to its reduction are currently lacking. In this work we expose the shortcomings of the classical contact resistance model in describing contacts to 2D materials, and offer a correction based on the addition of a lateral pseudo-junction resistance component (Rjun). We use a combination of unique contact resistance measurements to experimentally characterize Rjun for Ni contacts to monolayer MoS2. We find that Rjun is the dominating component of the contact resistance in undoped 2D devices and show that it is responsible for most of the back-gate bias and temperature dependence. Our corrected model and experimental results help understand the underlying physics of state-of-the-art contact engineering approaches in the context of minimizing Rjun.

We discuss the role of aluminum oxide (i.e. Al2O3 when stoichiometric) for transistors and sensors based on oxide semiconductors such as InGaZnO (IGZO) and two-dimensional (2D) semiconductors, such as monolayer MoS2. Aluminum oxide is a well-known capping and dielectric layer in semiconductor technology typically deposited by atomic-layer deposition (ALD), which offers a dense and high-quality film with low gas permeability even when deposited on flexible substrates. However, when deposited at low temperature (< 200°C), aluminum oxide can include a significant amount of fixed charges and defects, which lead to unusual charge trapping and doping effects in semiconductor devices. For example, such charge trapping can cause (apparent) sub-60 mV/decade subthreshold swing at room temperature in IGZO transistors, but can also lead to potential applications in neuromorphic computing. We also discuss effective doping (~1013 cm-2) of 2D semiconductors by thin ALD-grown non-stoichiometric AlOx capping layers. This is achieved with an aluminum seed layer, which enables uniform growth of the subsequently deposited ALD film. This approach leads to a negative shift in threshold voltage, record on-state current (~700 μA/μm) in a monolayer semiconductor, and drastic reduction in contact resistance. Finally, we investigate the passivation effects of Al2O3 capping, which limits the interaction of the underlying semiconductors with ambient air and moisture. We demonstrate improved response in MoS2 temperature sensors and long-term stability in flexible MoS2 transistors (8 months). Further, we evaluate the effects of Al2O3 passivation on IGZO transistors after aging for 80 months.

The expected high performance of graphene-based electronics is often hindered by lack of adequate doping, which causes low carrier density and large sheet resistance. Many reported graphene doping schemes also suffer from instability or incompatibility with existing semiconductor processing. Here we report ultrahigh and stable ${p}$ -type doping up to $\sim 7\times 10 ^{13}$ cm−2 ( $\sim 2\times 10 ^{21}$ cm−3) of monolayer graphene grown by chemical vapor deposition. This is achieved by direct polycrystalline MoO3 growth on graphene using a rapid flame synthesis technique. With this approach, the metal-graphene contact resistance for holes is reduced to $\sim 200~\Omega \cdot \mu \text{m}$ . We also demonstrate that flame-deposited MoO3 provides over $5\times $ higher doping of graphene, as well as superior thermal and long-term stability, compared to electron-beam deposited MoO3.

Metal contacts are a key limiter to the electronic performance of two-dimensional (2D) semiconductor devices. Here, we present a comprehensive study of contact interfaces between seven metals (Y, Sc, Ag, Al, Ti, Au, Ni, with work functions from 3.1 to 5.2 eV) and monolayer MoS2 grown by chemical vapor deposition. We evaporate thin metal films onto MoS2 and study the interfaces by Raman spectroscopy, X-ray photoelectron spectroscopy, X-ray diffraction, transmission electron microscopy, and electrical characterization. We uncover that (1) ultrathin oxidized Al dopes MoS2 n-type (>2 × 1012 cm-2) without degrading its mobility, (2) Ag, Au, and Ni deposition causes varying levels of damage to MoS2 (e.g. broadening Raman E' peak from <3 to >6 cm-1), and (3) Ti, Sc, and Y react with MoS2. Reactive metals must be avoided in contacts to monolayer MoS2, but control studies reveal the reaction is mostly limited to the top layer of multilayer films. Finally, we find that (4) thin metals do not significantly strain MoS2, as confirmed by X-ray diffraction. These are important findings for metal contacts to MoS2 and broadly applicable to many other 2D semiconductors.

The future scaling of semiconductor devices can be continued only by the development of novel nanofabrication techniques and atomically thin transistor channels. Here we demonstrate ultra-scaled MoS2 field-effect transistors (FETs) realized by a shadow evaporation method which does not require nanofabrication. The method enables large-scale fabrication of MoS2 FETs with fully gated  ∼10 nm long channels. The realized ultra-scaled MoS2 FETs exhibit very small hysteresis of current–voltage characteristics, high drain currents up to  ∼560 A m−1, very good drain current saturation for such ultra-short devices, subthreshold swing of ∼120 mV dec−1, and drain current on/off ratio of ∼106 in air ambient. The fabricated ultra-scaled MoS2 FETs are also used to realize logic gates in n-type depletion-load technology. The inverters exhibit a voltage gain of  ∼50 at a power supply voltage of only 1.5 V and are capable of in/out signal matching.

As traditional device scaling slows down, three-dimensional (3D) integrated circuits (ICs) are needed to continue Moore’s Law advancements. We show that two-dimensional (2D) semiconductors are promising for heterogeneously integrated 3D ICs owing to their atomically thin nature and unique processing, thermal, and device capabilities.

Phase change memory (PCM) is an emerging data storage technology; however, its programming is thermal in nature and typically not energy-efficient. Here, we reduce the switching power of PCM through the combined approaches of filamentary contacts and thermal confinement. The filamentary contact is formed through an oxidized TiN layer on the bottom electrode, and thermal confinement is achieved using a monolayer semiconductor interface, three-atom thick MoS2. The former reduces the switching volume of the phase change material and yields a 70% reduction in reset current versus typical 150 nm diameter mushroom cells. The enhanced thermal confinement achieved with the ultra-thin (similar to 6A degrees) MoS2 yields an additional 30% reduction in switching current and power. We also use detailed simulations to show that further tailoring the electrical and thermal interfaces of such PCM cells toward their fundamental limits could lead up to a sixfold benefit in power efficiency. Published under license by AIP Publishing.

Flexible electronics could greatly benefit from the realization of large-scale field-effect transistors (FETs) based on two-dimensional (2D) materials that exhibit high carrier mobility, flexibility, and transparency [1]. As high-quality 2D materials are synthesized at high temperatures $> 500\ {}^{\circ}\mathrm{C}$, they must rely on scalable processes for transfer to flexible substrates after growth. However, such transfer processes typically transfer the 2D material using scaffolds of poly(methyl methacrylate) (PMMA) and immersion in corrosive solutions, which can damage the 2D film and leave unwanted residues [2].

Here we propose a new wide band gap logic circuitry providing emerging power electronics with reliable logic control capabilities with 500 MHz+ switching speeds and withstanding 300V+. Particularly, a three-stage ring oscillator composed of NMOS (μe = 1000 cm2/V-s) and PMOS (μh = 250 cm2/V-s) cubic phase GaN devices (with VT of 0.77 V and –0.84 V, respectively) is simulated. The propagation delay is minimized by optimizing the width-to-length ratio (W/L) between the NMOS and PMOS devices. Transient response of the simulation illustrates the ability of the CMOS inverter to operate at a maximum frequency of 1.22 GHz with a full voltage swing between VDD of 2.5 V and 0 V. The proposed cutting-edge p-channel GaN high hole mobility transistor (HHMT) solves one of the most longstanding problems in power electronics and constitutes the basis of an innovative reduced total life cycle cost that will serve as the cornerstone of the next generation of integrated, scalable, and reliable power systems.

Mos 2 is a two-dimensional (2D) semi-conductor which is now considered as a channel material in 2D FETs [1]-[3]. Recently we found that single-layer (1L) Mos 2 FETs grown by chemical vapour deposition (CVD) and encapsulated with high-quality Al 2 O 3 layer exhibit superior performance and reliability compared to all previously reported 2D FETs [2]. However, while the I on / I off ratio (~10 9 ) of the devices [2] already fulfills commercial standards, their reliability is still poorer than for Si devices [4]. In order to understand the physical origin of these aspects, here we analyze the impact of annealing at 300°C and Al 2 O 3 deposition on the performance and hysteresis dynamics of 1L MoS 2 FETs.

In this work we investigate design parameters enabling normally-off operation of zincblende (ZB-) phase AlXGa((1-X)) N/GaN high electron mobility transistors (HEMTs) via Synopsys Sentaurus Technology Computer Aided Design (TCAD). As ZB-phase III-nitrides are polarization-free, the 2D electron gas (2DEG) channel at the AlXGa(1-X) N/GaN heterojunction is formed through intentional delta-doping part of the AlXGa(1-X) N barrier layer. The impact of each of the design parameters (i.e. Al-content and thickness ofAl(X)Ga((1-X)) N barrier; d-doping location (within the AlXGa(1-X) N barrier), d-doped AlXGa(1-X) N layer thickness and its doping amount; gate metal) are studied in detail and design trade-offs are reported. We show that work function of the gate metal impacts normally-off behavior and turn-on voltage considerably. Our results suggest that Al-content of 35% or less in the AlXGa(1-X) N barrier results in a normally-off behavior whereas AlXGa(1-X) N barrier thickness is effective in controlling the turn-on voltage. Overall, we provide design guidelines in controlling the normally-on/-off operation, threshold voltage, and 2DEG density in ZB-phase AlGaN/GaN HEMT technology.