Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The interconnect stack also features a very thick Metal-9 layer to provide a low resistance path for the power and I/O routing. The combined interconnect stack provides high performance and reliability and supports a Pb-free 45nm process.

The benefits of copper (Cu) die-side bumps for flip chip application are well known and have been sought for more than a decade. However, the introduction of fragile low-k interlayer dielectrics (ILD's) into back end interconnect architectures have made integrating copper bumps challenging, i.e. low-k ILD cracking that often leads to partial or complete die failure. For the 65nm technology node, Intel has successfully incorporated copper die-side bumps mated to eutectic tin-lead (SnPb) package-side bumps in high volume manufacturing (HVM). Advantages of using copper die bumps include lowering the bump critical dimension (CD) floor, continued downward scaling of passivation opening size, a drastically simplified underbump metallization (UBM) scheme that projects to improved electromigration resistance, and extensions to higher 10 densities. This paper will discuss some of these gains

The thermomechanical interaction of organic flip chip assembly is primarily driven by the coefficient of thermal expansion (CTE) mismatch between die and package. This, in addition to emerging constraints like mechanically weaker silicon inter-layer dielectrics, lead free assembly and tighter bump pitch, etc., significantly increase the assembly yield and reliability challenges. Electrically sensitive short loop assembly test vehicles with representative product design features provide quick data turn and more coverage than live products to address these interconnect concerns. Yield and reliability data plus stress modeling and experimental measurements from assembly test vehicles highlight the importance of silicon and package test structures to understand die to package CTE mismatch induced stress, helping to identify the weak links in packaging architecture from materials, process and design.