Product differentiation is expected to accelerate and will encompass integration of product functionality into single and multiple die on package as well as multiple die/packages on board. Novel packaging designs will lead to incorporation of new materials and processes from which a comprehensive understanding of operating conditions at system and subcomponent level will be required to ensure reliability at minimum impact to cost & performance. Reliability tests, models and analysis must evolve to encompass emerging failure mechanisms and geometric effects not considered when standards were originally authored. This manuscript will show trends in packaging and materials along with examples of emerging failure mechanisms that need to be understood to ensure reliability in highly integrated products.

IC components are exposed to moisture and thermal cycles during chip-package-board assembly and in their end use conditions. Moisture exposure influences the mechanical integrity of silicon backend dielectrics, assembly/packaging materials and packages. Reliability performance under accelerated stresses that simulate use conditions are often a critical factor in choice of materials, processing options and design rules. A complete assessment of the cumulative environmental exposure from chip-package assembly, shipment/storage, board system assembly, through end-customer use is required to guarantee product performance and reliability. This paper will detail these end user environments and use failure mode/mechanism specific acceleration models to develop accurate accelerated life testing plans and requirements. These requirements will then be compared to JEDEC standards based requirements and a need for re-calibration of these standards to more appropriate temperatures and stress durations will be highlighted.

Interconnect dielectric reliability challenges increase every generation due to dimension scaling and pursuing of lower K dielectrics for performance. In this paper, TDDB reliability characteration, process innovation, process control and product validation are presented based on Intel 32 nm technology node. In definition and technology development phase, extensive characterization and process innovation are needed to enable the proper choices of materials and processes. For any given healthy process and material set, the TDDB reliability is determined by via to line and line to line space distribution, and dominated by the tail distribution of dies with small space. Although different TDDB physical models such as E, root E or other models will project very different failure probability when extrapolating from high Efield to low Efield for the main population, the choice of models makes little difference for product level failure probability from the tail population because the Efield is already in the range of that used for accelerated stressing. Since product failure rate is dominated by tail population, more focus has been given to this area in terms of process development and control. Novel self-aligned via patterning process has been developed for 32 nm technology and significantly improved via to line space and thus the low K TDDB performance. In addition, to ensure superior quality and reliability, extensive process window and product level validation through extended life test are necessary to capture and eliminate worse case process and product corners. A scaling trend and potential path to enable continuing scaling are highlighted.

A 4Kbit high-density PROM array design featuring a high-volume manufacturable metal-fuse technology in 32nm high-k metal-gate CMOS is introduced. In contrast to a traditional salicided polysilicon based 2-D fuse cell, the metal-fuse technology enables a 3-D cell topology with program device and fuse element stacked on each other, achieving a 1.37µm2 cell footprint. The 128-row by 32-column array with an asymmetric tunable static sense scheme can operate down to 0.5V and provides multi-bit programming capability. A 100% programming success rate at 2V-1µs condition is achieved along with security protection.

Interconnect process features are described for a 32nm high performance logic technology. Lower-k, yet highly manufacturable, Carbon-Doped Oxide (CDO) dielectric layers are introduced on this technology at three layers to address the demand for ever lower metal line capacitance. The pitches have been aggressively scaled to meet the expectation for density, and the metal resistance and electromigration performance have been carefully balanced to meet the high reliability requirements while maintaining the lowest possible resistance. A new patterning scheme has been used to limit any patterning damage to the lower-k ILD and address the increasingly difficult problem of via-to-metal shorting at these very tight pitches. The interconnect stack has a thick Metal-9 layer to provide a low resistance path for the power and I/O routing that has been carefully scaled to maintain a low resistance. The combined interconnect stack provides high density, performance, and reliability, and supports a Pb-free 32nm process.

A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for any 32nm or 28nm logic technology. NMOS drive currents are 1.62mA/um Idsat and 0.231mA/um Idlin at 1.0V and 100nA/um Ioff. PMOS drive currents are 1.37mA/um Idsat and 0.240mA/um Idlin at 1.0V and 100nA/um Ioff. The impact of SRAM cell and array size on Vccmin is reported.

A leading edge 45 nm CMOS system-on-chip (SOC) technology using Hafnium-based high-k/metal gate transistors has been optimized for low power products. PMOS/NMOS logic transistor drive currents of 0.86/1.08 mA/um, respectively, have been achieved at 1.1 V and off-state leakage of 1 nA/um. Record RF performance for a mainstream 45 nm bulk CMOS technology has been achieved with measured fT/fMAX values of 395 GHz/410 GHz for NMOS and 300 GHz/325 GHz for PMOS with 28 nm Lgate transistors. HV I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OTP fuses are employed for HV I/O, analog and RF circuit integration.

Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The interconnect stack also features a very thick Metal-9 layer to provide a low resistance path for the power and I/O routing. The combined interconnect stack provides high performance and reliability and supports a Pb-free 45nm process.

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum 2 , and on multiple microprocessors.

Thermal strains and electromigration can cause voids to grow in conductor lines on semiconductor chips. This long-standing failure mode is exacerbated by the recent introduction of low-permittivity dielectrics. We describe a method to calculate the volume of a saturated void (VSV), attained in a steady state when each point in a conductor line is in a state of hydrostatic pressure, and the gradient of the pressure along the conductor line balances the electron wind. We show that the VSV will either increase or decrease when the coefficient of thermal expansion of the dielectric increases and will increase when the elastic modulus of the dielectric decreases. The VSV will also increase when porous dielectrics and ultrathin liners are used. At operation conditions, both thermal strains and electromigration make significant contributions to the VSV. We discuss these results in the context of interconnect design.

This paper describes a framework to study the initiation and arrest of an interfacial crack, using a combination of experiment and computation. We consider a test configuration widely used in the microelectronic industry: a sample of two substrates bonded by a stack of thin films, with a pre-crack in one of the substrates, perpendicularly impinging upon the films. When the sample is loaded to a critical level, the pre-crack initiates a new crack on one of the interfaces in the sample. The new crack often runs rapidly on the interface for a considerable length, and then arrests. We introduce a quantity, the initiation energy, to characterize the condition under which the pre-crack initiates the interfacial crack. The initiation energy is independent of the test configuration on the scale of the substrates, but changes greatly with the materials and stacking sequence of the films. We measure the initiation energy experimentally, interpret the data using mechanistic models, and use the initiation energy to predict the arrest crack length.

We explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130-nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing pose serious challenges to the implementation of such materials in high-volume manufacturing. We consider the cases of two ILD materials, carbon-doped silicon dioxide and low-k spin-on-polymer, to illustrate the impact of the ILD choice on the process technology and reliability of copper interconnects.

A new, computationally efficient model for silicon hole mobility under stress is presented. The model predicts the modulation of hole mobility by stress under arbitrary stress conditions, channel orientations, and fields. The model uses a simplified k-space description of the silicon valence band, while preserving the relevant symmetry properties. The shape of the bandstructure is a function of the shear and biaxial stress components in the crystal coordinates, and the mobility tensor is computed for the given stress conditions. The model is based on the results of a rigorous silicon valence bandstructure calculation, and is calibrated and tested using extensive wafer-bending data.

For a crack in a structure, the crack driving force G is the reduction of the elastic energy in the structure, associated with the crack extending per unit area. In principle, G can be calculated by solving a boundary value problem. In practice, however, such a calculation is prohibitively difficult for integrated structures of complex architectures, diverse materials and small features. The calculated G is suspect when deformation properties and residual stress fields are poorly characterized. On the other hand, it costs little to make many replicates of an integrated structure, so that massive testing is affordable. We describe an experimental method to measure G. A crack, assisted by molecules (e.g., moisture) in the environment, often extends at a velocity V increasing with the crack driving force G. The V-G function is specific to a given material and its environment. Once determined, the same function applies when this material is integrated in a structure with other materials, provided environmental molecules reach the crack front. In the integrated structure, an observed crack velocity, together with the known V-G function, provides a reading of the crack driving force. The observed crack velocity can be used to measure deformation properties of ultrathin films. We also describe a procedure to measure the crack driving force G(R) due to the residual stress field in the integrated structures, even when G(R) by itself is too low for the crack to extend at a measurable velocity.

Recent attention has been given to metal–oxide–semiconductor field-effect transistor (MOSFET) device designs that utilize stress to achieve performance gain in both n-type MOSFETs (NMOS) and p-type MOSFETs (PMOS). The physics behind NMOS gain is better understood than that of PMOS gain, which has received less attention. In this letter, we describe the warping phenomena which is responsible for the gain seen in [110] uniaxially stressed PMOS devices on [100] orientated wafers. We also demonstrate that shear uniaxial stress in PMOS is better suited to MOSFET applications than biaxial stress as it is able to maintain gain at high vertical and lateral fields.

— In this work we discuss how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper as the metal of choice at the 130nm technology node mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of advanced interconnects. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing, pose serious challenges to the implementation of such materials in high volume manufacturing. We will consider the cases of two ILD materials; carbon-doped silicon dioxide (CDO) and low-k spin-on-polymer to illustrate the impact of ILD choice on the process technology and reliability of copper interconnects.

We study electromigration in copper lines encapsulated in an organosilicate glass. A line fails when a void near the upstream via grows to a critical volume. We calculate the void volume as a function of time. The statistical distribution of the critical volume (DCV) is taken to be independent of testing variables, such as line length and electric current density. By contrast, the distribution of the lifetime (DLT) strongly depends on these testing variables. We deduce the DCV from the experimentally measured DLT. Once deduced, the DCV can predict the DLT under untested conditions.

The electromigration lifetime is measured for a large number of copper lines encapsulated in an organosilicate glass low-permittivity dielectric. Three testing variables are used: the line length, the electric current density, and the temperature. A copper line fails if a void near the upstream via grows to a critical volume that blocks the electric current. The critical volume varies from line to line, depending on line-end designs and chance variations in the microstructure. However, the statistical distribution of the critical volume (DCV) is expected to be independent of the testing variables. By contrast, the distribution of the lifetime (DLT) strongly depends on the testing variables. For a void to grow a substantial volume, the diffusion process averages over many grains along the line. Consequently, the void volume as a function of time, V(t), is insensitive to chance variations in the microstructure. As a simplification, we assume that the function V(t) is deterministic, and calculate this function using a transient model. We use the function V(t) to convert the experimentally measured DLT to the DCV. The same DCV predicts the DLT under untested conditions.