We describe here performance enhancement to Intel's 14nm high-performance logic technology interconnects and back end stack and introduce the SOC technology family of interconnects. Enhancement includes improved RC performance and intrinsic capacitance for back end metal layers over a range of process versions and metal stacks offered for optimal cost and density targeted for various applications.

A leading edge 14 nm SoC platform technology based upon the 2 nd generation Tri-Gate transistor technology [5] has been optimized for density, low power and wide dynamic range. 70 nm gate pitch, 52 nm metal pitch and 0.0499 um 2 HDC SRAM cells are the most aggressive design rules reported for 14/16 nm node SoC process to achieve Moore's Law 2x density scaling over 22 nm node. High performance NMOS/PMOS drive currents of 1.3/1.2 mA/um, respectively, have been achieved at 0.7 V and 100 nA/um off-state leakage, 37%/50% improvement over 22 nm node. Ultra-low power NMOS/PMOS drives are 0.50/0.32 mA/um at 0.7 V and 15pA/um Ioff. This technology also deploys high voltage I/O transistors to support up to 3.3 V I/O. A full suite of analog, mixed-signal and RF features are also supported.

We describe interconnect features for Intel's 22nm high-performance logic technology, with metal-insulator-metal capacitors and nine layers of interconnects. Metal-1 through Metal-6 feature a new ultra-low-k carbon doped oxide (CDO) and a low-k etch stop. Metal-7 and Metal-8 use a low-k CDO. New materials and process optimization provide 13-18% capacitance improvement. Single-exposure patterning for 80nm pitch layers makes the process cost-effective.

June 12, 2012 – Intel Corporation is delivering myriad presentations, panel discussions and demonstrations at this year’s VLSI Symposia. A highlight paper discloses new details about Intel’s 22nm process – the industry’s first fully depleted 3-D tri-Gate technology with superior low voltage and low power capabilities. Other Intel papers describe innovations in reducing power consumption for graphics processing, advances in transistors made with compound semiconductors, a viable option for future ultra-low power transistors, fundamental leaps in energy-efficient computing and integrated digital radio and SoC technology.

Interconnect process features are described for a 45nm high performance logic technology. Through extensive use of highly manufacturable carbon doped oxide low-k dielectric layers and aggressive scaling of the SiCN etch stop film the Metal-1 to Metal-8 interconnect stack demonstrates a 10% average capacitance reduction over the 65nm process. The interconnect stack also features a very thick Metal-9 layer to provide a low resistance path for the power and I/O routing. The combined interconnect stack provides high performance and reliability and supports a Pb-free 45nm process.

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate dielectric, dual band edge workfunction metal gates and third generation strained silicon, resulting in the highest drive currents yet reported for NMOS and PMOS. The technology also features trench contact based local routing, 9 layers of copper interconnect with low-k ILD, low cost 193 nm dry patterning, and 100% Pb-free packaging. Process yield, performance and reliability are demonstrated on 153 Mb SRAM arrays with SRAM cell size of 0.346 mum 2 , and on multiple microprocessors.

A 45nmlogic technology isdescribed that forthefirst time incorporates high-k ±metal gate transistors inahigh volume manufacturing process. Thetransistors feature 1.OnmBOT6 high-k gatedielectric, dualbandedgeworkfunction metal gates andthird generation strained silicon, resulting inthe highest drive currents yetreported forNMOS andPMOS. Thetechnology alsofeatures trench contact basedlocal routing, 9layers ofcopper interconnect withlow-k ILD,low cost193nmdrypatterning, and1000o Pb-free packaging. Process yield, performance andreliability aredemonstrated on153MbSRAM arrays withSRAM cell size of0.346gtm2, Fig. 2TEMofHigh-k +Metal Gatetransistor stack andonmultiple microprocessors.

The impact of etch-stop (ES)/Cu interfacial chemistry on adhesion and electromigration (EM) has been systematically investigated by varying Cu surface chemistry, etch-stop film chemistry, metal capping layers, and thermal annealing conditions. Adhesion and EM improvement directly correlate with reducing interfacial oxygen for all the systems studied. While the adhesion of freshly deposited ES films strongly depends on the Cu surface chemistry and ES deposition conditions, the hermeticity of the ES film significantly impacts the film and interface chemistry during subsequent processing and thermal cycles, consequently affecting the long term stability of adhesion and electromigration performance. The mechanism for the correlation and material properties governing the interfacial chemistry will be discussed.

A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic is presented. Transistor gate length is scaled down to 35nm while not scaling the gate oxide as a means to improve performance and reduce power. Increased NMOS and PMOS drive currents are achieved by enhanced channel strain and junction engineering. 193nm lithography along with APSM mask technology is used on critical layers to provide aggressive design rules and a 6-T SRAM cell size of 0.57mum(2). Process yield, performance and reliability are demonstrated on a 70 Mbit SRAM test vehicle with >0.5 billion transistors.

PdAl was selected as a reactive contact to n-(In0.52Al0.48)As with the intention of forming a thin, AlAs-enriched interlayer of graded (In1−xAlx)As semiconductor alloy, following rapid thermal annealing. Selection of PdAl was based on the experimentally established existence of a quasi-reciprocal phase relationship. A Schottky barrier enhancement of 0.07 eV (measured by current-voltage (I-V)) and 0.09 eV (measured by capacitance-voltage (C-V)) was found following a 1-min anneal at 450°C. High-resolution transmission electron microscopy (HRTEM) examination showed the presence of an edge dislocation in the interlayer alloy, suggesting an enrichment of AlAs. Schottky barrier enhancement is in qualitative agreement with the prediction of the combined thermodynamic/kinetic model.