Emerging 3D nanoelectronic and nanophotonic architectures require dielectric integration with nanometric thickness control to enable vertical stacking and the deposition of strain-sensitive functional layers. High planarity combined with precise control of the supporting dielectric thickness is essential to deposit thin materials without inducing strain, deformation, or performance degradation. Conventional planarization approaches based on thick SiO2 deposition and chemical-mechanical polishing (CMP) offer limited thickness precision at the nanometric scale. Although Spin-On Glass (SOG) combined with etch-back processes improves thickness control, it has not yet enabled geometry-independent nanoscale planarity across dense 3D nanostructure networks. Here, we demonstrate a geometry-independent planarization strategy that embeds nanostructures of various dimensions and densities within a dielectric matrix while achieving nanometric control of both layer thickness and surface flatness. The approach relies on successive HSQ spin-on glass depositions that progressively smooth surface nonuniformities, combined with calibrated thickness adjustment through reactive ion etching assisted by laser interferometry for controlled etch-stop positioning. Multicycle HSQ deposition reduces surface height variations from approximately 40 nm to within ±2 nm across diverse nanostructure geometries. Deterministic positioning of the SiO2 surface relative to embedded silicon nanostructures is achieved with an accuracy of ±3-5 nm. The interface precision is validated using monolayer MoSe2 as a strain-sensitive optical probe due to its strain-tunable optical properties. Photoluminescence measurements demonstrate controlled near-field coupling for separations below approximately 15 nm while achieving minimal residual strain (<0.02%), in contrast to nonplanarized configurations exhibiting higher strain levels (∼0.06-0.08%). This planarization provides a platform for the strain-controlled integration of 2D materials and advanced thin films onto embedded 3D nanostructures.

The continuous scaling of semiconductor devices has driven the evolution of transistor architectures beyond planar configurations. Vertical Gate-All-Around (V-GAA) nanowire transistors are emerging as a promising alternative to conventional FinFETs, offering enhanced performance and reduced short-channel effects, particularly for advanced CMOS and post-CMOS technologies. However, conventional fabrication methods for V-GAA transistors often rely on lift-off techniques for metal deposition, which lead to asymmetrical source and drain contacts, increasing access resistance and limiting device performance. In this work, we present a scalable, microelectronic-compatible fabrication process for Junction-Less Vertical Gate-All-Around Nanowire Field-Effect Transistors (JL-VGAA FETs), which allows the construction of high-performance logic cells (NOT, NOR, NAND) with excellent electrical characteristics. The fabrication process involves a novel, lift-off-free technique for creating symmetrical silicided source and drain contacts, which are crucial for minimizing access resistance and improving yield. This method includes a two-step oxidation process: the first step patterns the bottom metal lines, and the second step selectively removes the oxide to establish the gate oxide layer on the nanowires. After forming the nanowires using top-down lithography and etching, platinum silicide (PtSi) contacts are formed through a self-aligned silicidation process. The resulting FETs exhibit reduced contact resistance and enhanced drive current. Electrical measurements show that the drive current (I_ON) scales linearly with the number of nanowires, with values reaching 665 μA/μm for 34 nm diameter nanowires and 477 μA/μm for 27 nm diameter nanowires at V_DS = -1.1 V, demonstrating the process's scalability and robustness. We applied this fabrication process to develop logic cells based on a p-type silicon substrate, utilizing a negative logic convention (logic '0' = -1V, logic '1' = 0V). The architecture's versatility is demonstrated through the construction of a passive NOR gate, composed of two series-connected V-GAA FETs with a load resistor simulating the pull-up network of traditional CMOS logic. The NOR gate achieved a highly accurate logic response with a figure of merit (FOM defined as |V Y='1' – V Y='0' | / |V Ymin |; V Ymin being ideal response of a perfect logic gate) of 98.2%, showcasing minimal signal degradation. A passive NAND gate, formed by connecting two V-GAA FETs in parallel with a load resistor, also exhibited excellent performance. We further enhanced the design by incorporating an active NAND gate, where a supplementary FET is used to fine-tune the load resistance, resulting in an FOM of 94.5%. This work highlights the advantages of V-GAA nanowire transistors over conventional planar FinFET technologies, particularly in terms of device density and performance. By leveraging vertical integration, we achieve a significant reduction in logic gate footprint—over 50% compared to planar technologies—while maintaining high drive currents and strong electrostatic control. These results demonstrate the feasibility of scaling Junction-Less V-GAA nanowire FETs for high-density logic applications, offering a pathway to further advances in both CMOS and post-CMOS technologies. Figure 1: Electrical diagram (a) and 3D representation (b) of our active NAND device integrating three sets of JL-VGAA-FETs whose essential nanowire is shown in TEM (c). Corresponding A/B inputs and Y output are shown in (d) corresponding to an active NAND logic. Acknowledgement This work was supported by the FVLLMONTI project funded by European Union’s Horizon 2020 research and innovation program under grant agreement N◦101016776 and by the LAAS-CNRS micro and nanotechnologies platform, a member of the Renatech French national network. Figure 1

Research on transistors with various architectures is crucial for developing high-performance, compact devices, as they improve the functionality of integrated circuits within the same or smaller footprint. Simulation studies have shown that transistors fabricated using a U-shape channel have a higher functionality as their natural geometry enables the realization of gate-all-around structures and long channel lengths within a small footprint. The experimental realization of the transistor is essential for exploring circuit applications. This paper presents the process integration route and the first experimental results of a U-shape ambipolar Schottky barrier field effect transistor. Also, a detailed explanation of the challenges in fabricating a 3D transistor and the improvement steps are given. The fabricated device demonstrates highly symmetrical on-currents for both p- and n-branches. Self-aligned contact formation and atomic force microscopy imaging are used to simplify fabrication and facilitate 3D structural monitoring. In addition, the formation of self-aligned contacts in the proposed device architecture is significantly simplified compared to traditional 3D architectures. TCAD simulations are also performed to support the experimental findings and demonstrate the device's future potential and scalability. In conclusion, it effectively addresses the challenges of the fabrication of 3D transistors and drives innovations in device design with its silicon-on-insulator body.

The rapid growth of semiconductor technology over the past decades has highlighted the need to overcome the limitations of traditional computer designs. This conventional architecture faces challenges related to data transfer, caused by the separation of memory and processing units, commonly referred to as the Von Neumann bottleneck. To address this issue, the integration of non-volatility into processing devices has been explored, enabling data storage and logic operations to be performed in the same location-a concept known as Logic-in-Memory architectures. A promising solution in this direction is the integration of ferroelectric materials, which can function as memory elements through their remanent polarization within processing devices. Over the past decade, hafnium zirconium oxide (HZO) has emerged as a standout candidate [1], owing to its CMOS compatibility and adaptability to miniaturization while retaining its ferroelectric properties. The two most prevalent approaches for achieving non-volatility with ferroelectric HZO are FeRAM and FeFET. While ferroelectric random-access memory (FeRAM) offers fast switching characteristics, its destructive read-out process limits its practicality as a non-volatile element and poses scalability challenges. Conversely, HZO-based FeFETs present a compelling alternative, leveraging the non-volatility of ferroelectric HZO while capitalizing on the extreme scalability of FET technology. Although extensive research exists on planar devices, integration into advanced Gate-All-Around (GAA) technology remains a significant challenge. This study focuses on the transition from thin planar 10 nm HZO layer with ferroelectric properties to its vertical integration in Gate-All-Around technology [2], aiming toward the realization of a Vertical GAA FeFET. First, a comprehensive study of the gate stack (TiN-HZO-thin interfacial layer SiO2-Si) was conducted, encompassing morphological, physical, and electrical characterizations. The initial stack comprises a 10 nm HZO layer on a Si substrate with a precisely grown 1.5 nm SiO 2 interfacial layer and TiN as a capping layer, forming a MIS capacitor. The crystallization of the HZO layer at annealing temperatures as low as 400°C was demonstrated (Figure 1a), with the orthorhombic phase responsible for ferroelectric properties was identified via GIXRD analysis (Figure 1b). The ferroelectric properties of the HZO layers were characterized using fast pulse electrical methods on MIS capacitors, achieving remanent polarization values up to 28 μC/cm² at 600°C (Figure 1c-d) and a coercive field of approximately 5 MV/cm. This optimized gate stack configuration was subsequently applied to vertical nanostructured channels (nano-sheets/nanowires). The conformality of the layer deposition, crucial for vertical device fabrication, was verified using TEM cross-sectional observations, ensuring no interdiffusion at the SiO2/HZO interface (Figure 1e-f). Due to the 3D nature of nanowires, conventional GIXRD methods were unsuitable for crystalline phase identification. To overcome this, an innovative technique combining 4DSTEM observations with machine learning was developed to map and identify the crystalline phases of individual grains in the HZO layer. This approach successfully achieved full mapping of the HZO grains on vertical nanowires, identifying orthorhombic HZO grains as the dominant phase. With the crystalline phase confirmed for HZO on vertical nanowires through 4DSTEM, two parallel fabrication pathways for Vertical GAA FeFETs were explored. The first pathway, known as the gate-first approach, integrates HZO during the initial stages of nanowire formation, leveraging the excellent layer conformality. The second pathway introduces HZO after alloy contact formation, prioritizing the quality of alloy contacts in the device. Each approach presents unique fabrication challenges, which are discussed, paving the way for improved control of thin HZO layers in vertical device fabrication. This study highlights the critical steps required to understand and leverage the nanoscale properties of HZO for the realization of Vertical Nanowire GAA FeFETs. By addressing key challenges in scalability, process complexity, and device performance, HZO-based vertical nanowire FeFETs hold immense promise for applications such as energy-efficient data storage and neuromorphic computing, where memory and computation coalesce to emulate brain-like processing capabilities [3]. [1] Müller et al. (2012). Ferroelectricity in Simple Binary ZrO 2 and HfO 2. Nano letters. 12. 4318-23. 10.1021/nl302049k. [2] Kumar et al. (2024). Logic Gates Based on 3D Vertical Junctionless Gate-All-Around Transistors with Reliable Multilevel Contact Engineering. Nano letters. 24. 10.1021/acs.nanolett.3c04180. [3] Lederer et al. (2021). Ferroelectric Field Effect Transistors as a Synapse for Neuromorphic Application. IEEE Transactions on Electron Devices. 68. 2295 - 2300. 10.1109/TED.2021.3068716. This work is funded by the European Comission through the H2020 FVLLMONTI project and supported by the Renatech French National Network Figure 1

Vertical silicon nanowire transistors are among the most promising device concepts for future low-power electronics due to their gate-all-around nature as well as their 3D stacking potential. In this work we review the current status of transistor fabrication on vertical silicon nanostructures and identify the most important challenges for successful process integration. Channel patterning, source/drain contact formation, gate-deposition and spacer engineering are identified as key steps independent on the actual process integration sequence. We conclude the paper with two emerging device examples and discuss the influence of the processing challenges on the transistor design.

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube ((NC2)-C-2), which is specifically designed to execute complex machine learning tasks in a 3D technology, in order to provide the high computing power and ultra-high efficiency needed for future edgeAI applications. We showcase its effectiveness by targeting the challenging class of Transformer ANNs, tailored for Automatic Speech Recognition and Machine Translation, the two fundamental components of speech-to-speech translation. To gain the full benefit of the accelerator design, we develop disruptive vertical transistor technologies and execute design-technology-co-optimization (DTCO) loops from single device, to cell and compute cube level. Further, a hardware-software-co-optimization is executed, e.g. by compressing the executed speech recognition and translation models for energy efficient executing without substantial loss in precision.

Vertical gate-all-around (V-GAA) represents the ultimate configuration in the forthcoming transistor industry, but it still encounters challenges in the semiconductor community. This paper introduces, for the first time, a dual-input logic gate circuit achieved using 3D vertical transistors with nanoscale sub-20-nm GAA, employing a novel technique for creating contacts and patterning metallic lines at the bottom level without the conventional lift-off process. This involves a two-step oxidation process: patterning the first field oxide to form bottom metal lines and then creating the gate oxide layer on nanowires (NWs), followed by selective removal from the top and bottom of the nanostructures. VGAA-NW transistors, fabricated using the lift-off-free approach, exhibit improved yield and reduced access resistance, leading to an enhanced drive current while maintaining good immunity against short-channel effects. Finally, elementary two-input logic gates within a single cell, using VNW transistors, demonstrate novel possibilities in advanced logic circuitry design and routing options in 3D.

This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit-level simulations indicate a strong impact of temperature variation on functionality and figures of merits, such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements.

Gate-all-around (GAA) transistors are anticipated to have a substantial impact in achieving logic scaling in the nanometer technology node range, serving as a substitute for the current FinFET technology which lacks acceptable immunity against short channel effect at such miniaturization. GAA transistors offer several advantages over older transistor designs, such as better performance, lower leakage, and reduced energy consumption. This makes them a more sustainable and environmentally friendly alternative to current architectures. In term of integration, vertical gate-all-around devices offer extreme density capability, surpassing equivalent planar technologies. Nevertheless, the development of vertical technology requires rethinking the entire development chain from design to technology. Here, we will present an overview of this technology with a particular focus on the engineering of 3D nanostructured channels and on the integration of S/D contacts on such vertical channels.

Understanding trap dynamics and formation of localized temperature hot-spots due to self-heating is crucial for the design optimization of emerging vertical junctionless nanowire transistors (VNWFET). This work investigates the operation of an 18 nm VNWFET technology, for the first time, leveraging pulsed current-voltage measurements. Results indicate increased trap activity as well as electrothermal effects with increasing pulse width. Multiphysics simulations are then used to provide a deeper insight into the nanoscale transport of the VNWFETs. We then incorporated these effects into the SPICE-compatible VNWFET compact model and further investigated the behaviors of trapping and electrothermal effects in basic logic circuits based on the compact model simulation.

This work presents a comprehensive analysis of electrothermal effects in emerging 3D vertical junctionless nanowire transistors (VNWFETs) using on-wafer measurements under a wide range of temperature and validated against numerical and compact model simulations. Experimental observations indicate an increase of the drain current with the temperature, conforming to the behavior of junctionless FETs. Multiphysics simulations reveal formation of temperature hot-spots that adversely affect thermal conductivity in smaller geometries. The VNWFET compact model was then modified to account for the underlying electro-thermal effects as well as dynamic self-heating. Model simulations and the experimental results at different measurement temperatures for different transistor geometries show good agreement. The developed SPICE-compatible compact model was then used for studying the impact of electrothermal effects on the performances of basic 3D logic circuits.

Devolvement of high-performance logic application in sub-20 nm technology node has gained significant attention due to their improved electrostatic and thermal control. In this work, we investigate electro-thermal transport in vertical junctionless nanowire transistors (VNWFET) at cryogenic temperatures to understand thermal effects in nanoscale regime. It highlights that heat dissipation and thermal stability are more efficient compared to planar Finfet configuration.

In this study, we demonstrate the effect of change of the sputtering power and the deposition pressure on the ignition and the combustion properties of Al/CuO reactive thin films. A reduced sputtering power of Al along with the deposition carried out at a higher-pressure result in a high-quality thin film showing a 200% improvement in the burn rate and a 50% drop in the ignition energy. This highlights the direct implication of the change of the process parameters on the responsivity and the reactivity of the reactive film while maintaining the Al and CuO thin-film integrity both crystallographically and chemically. Atomically resolved structural and chemical analyzes enabled us to qualitatively determine how the microstructural differences at the interface (thickness, stress level, delamination at high temperatures and intermixing) facilitate the Al and O migrations and impact the overall nano-thermite reactivity. We found that the deposition of CuO under low pressure produces well-defined and similar Al-CuO and CuO-Al interfaces with the least expected intermixing. Our investigations also showed that the magnitude of residual stress induced during the deposition plays a decisive role in influencing the overall nano-thermite reactivity. Higher is the magnitude of the tensile residual stress induced, stronger is the presence of gaseous oxygen at the interface. By contrast, high compressive interfacial stress aids in preserving the Al atoms for the main reaction while not getting expended in the interface thickening. Overall, this analysis helped in understanding the effect of change of deposition conditions on the reactivity of Al/CuO nanolaminates and several handles that may be pulled to optimize the process better by means of physical engineering of the interfaces.

This work investigates the combustion of porous Al/CuO thermites, i.e. nanolaminates fabricated with various densities of micron sized air-filled pores in the range of 0 20 vol%. High-speed videography and pyrometry of the high-temperature propagating flame were used to analyze the effect of porosity on propagation velocity. Incorporating micron sized pores in Al/CuO nanolaminates results in a faster burn rate (burn rate enhancement of 18% for pores loading of 20 vol%) while the flame temperature remains the same. Microscopic observations of the flame front in porous nanolaminates show hot-spots around each pore in the upstream of the flame but no advection. Conduction remains the dominant heat transfer mechanism in dense thermite configuration (80 % TMD) and the causes of burn rate enhancement when pores are

It was experimentally found that silica and gold particles can modify the combustion properties of nanothermites but the exact role of the thermal properties of these additives on the propagating combustion front relative to other potential contributions remains unknown. Gold and silica particles of different sizes and volume loadings were added into aluminum/copper oxide thermites. Their effects on the flame front dynamics were investigated experimentally using microscopic dynamic imaging techniques and theoretically via a reaction model coupling mass and heat diffusion processes. A detailed theoretical analysis of the local temperature and thermal gradients at the vicinity of these two additives shows that highly conductive inclusions do not accelerate the combustion front while poor conductive inclusions result in the distortion of the flame front (corrugation), and therefore produce high thermal gradients (up to 1010K.m-1) at the inclusion/host material interface. This results in an overall slowing down of the combustion front. These theoretical findings contradict the experimental observations in which a net increase of the flame front velocity was found when Au and SiO2particles are added into the thermite. This leads to the conclusion that the faster burn rate observed experimentally cannot be fully associated with thermal effects only, but rather on chemical (catalytic) and/or mechanical mechanisms: formation of highly-stressed zones around the inclusion promoting the reactant mixing. One additional experiment in which physical SiO2particles were replaced by voids (filled with Ar during experiment) to cancel the potential mechanical effects while preserving the thermal inhomogeneity in the thermite structure confirms the hypothesis that instead of pure thermal conduction, it is the mechanical mechanisms that dominate the propagation velocity in our specific Al/CuO multilayered films.

Reactive multilayer films are a high energy dense configuration for energetics widely studied for various pyrotechnic applications. The objective of this study is to investigate the influence of substrate-induced localized stress on the combustion properties of Al/CuO reactive thin films. Square microbumps are patterned on glass substrates to serve as embedded stressor elements. Stress-induced structural or morphological changes of the materials deposited around the microbumps are characterized using high-magnification transmission and scanning electron microscopy, providing simultaneous nanometer imaging resolution and detailed chemical analysis. The structural and chemical changes (appearance of reactant intermixing and voids) around the microbumps modify the energetic reservoir and the thermophysical properties of the film. The heat of reaction, the flame temperature and the effective thermal conductivity of the film are altered (loss of similar to 15%), leading to a global decrease in the material reactivity. The flame velocity of the film deposited on the substrate with microbumps drops by 9.2%, 32.4% and 48.7% for microbump heights of 0.15, 0.35 and 0.83 mu m, respectively. This work helps deepen the understanding of the effect of stress-induced strain on reactive film combustion properties and provides perspectives for controlling the reaction of reactive thin films by tailoring the strain distributions within the films.

A prior investigation by the authors demonstrated that incorporating 25% of copper complex (Cu(NH3)4(NO3)2) into Al/CuO nanothermite enables to produce highly-reactive gas-generating energetic composites for emerging micro-airbag applications. To further improve the decomposition of the copper complex into gaseous species (N2, O2, N2O), during the thermite reaction, we employed ball milling technique to diminish its grain size down to the nanoscale. Results show that premilling the copper complex i.e. refining its grains without much modifying their structures, increases the pressure generation and burn rate by a factor 1.5 and 2, respectively. It also maintains a high degree of performances along with a wider range of thermite to copper complex mass ratio.

We developed an Ultimate Security Device (USD) that can, in case of intrusion or external attack, blow up a safety-critical component such as memory device. The device consists of two active parts (1) a pyroMEMS ignites in a fraction of millisecond (2) a mass of reactive composite, both encapsulated into a printed hermetic cap and placed over the sensitive component to be protected. After the presentation of the design and integration of the USD, we demonstrated that 400 mg of reactive composite permits to irreversibly destroy the silicon chips (~118 mm3) in less than 10 ms. This ultimate security device provides a speedy and automatic response and can be programmed for tunable actions (generation of pressure burst, heat, chemical species) to implement relevant emergency safety responses.

Due to their narrow reflection peak as well as their compact structure, guided mode resonance filters (GMRFs) are attractive for many applications. In this work, we will demonstrate the possibility to modulate the properties of a GMRF by associating it with liquid crystals (LCs). By impregnating the diffraction grating with LCs, it is possible to switch between an active and an inactive state depending on the polarization of the light or the applied voltage. In this paper we fabricated and characterized the first diffraction order of LC-impregnated gratings with different periods (0.8–5.0 µm) and depths (120 and 840 nm) to test the ability of liquid crystals to adjust the diffraction properties. Finally, without voltage, more than 99.8% of initial diffraction could be turned off with a 90° rotation polarization whereas, by applying a voltage of 30 V; 90–99% of the initial diffraction is turned off according to the grating dimensions. The effect of the grating dimension (period, depth) on the diffraction modulation capacity will be discussed.