This work proposes a holistic framework to assess the impact of variation in advanced transistor technology, such as ageing, voltage drop and threshold voltage, on system-level reliability, consistently linking device, circuit, and architecture levels. At the device level, the impact of these variations is first evaluated and translated into timing variations on standard cells (e.g., delay distributions). Once the standard cells are characterized, path-delay modifications are analyzed at circuit level, and the resulting timing profiles are then propagated to an architectural model to quantify their impact at system level under realistic workloads. To demonstrate the proposed flow, an emerging vertical nanowire gate-all-around (VNWFET) technology, featuring excellent electrostatic control yet pronounced sensitivity to process-induced and design time variations fluctuation, is used to implement an energy-efficient systolic array accelerator. The target application is a convolutional neural network (CNN) representative of edge-AI inference workloads, mapped onto the systolic array with realistic operating conditions and timing constraints. Results show that the proposed framework accurately captures the propagation of variations-induced delays from devices up to application-level metrics, enabling the identification of vulnerable paths, quantification of performance and accuracy degradation, and exploration of design margins and mitigation strategies at an early design stage.

In this article, we report on the design and characterization of InP-DHBT analog multiplexer (AMUX)-driver integrated circuits (ICs) for next generation >= 200 Gbaud (GBd) metro/long-haul optical transceivers. We show that the transimpedance stage (TIS) loading of the AMUX selecting cell provides superior gainxbandwidth and linearity performances with respect to the commonly used resistive and cascode loads. Moreover, the driving clock amplitude and tail current of the selecting core are shown to be key parameters for the AMUX-driver design. The AMUX-drivers with TIS loading are fabricated in the III-V Lab's InP DHBT process, showing up to 200-GSa/s sampling rate, without any support of DSP. At 100 GSa/s and 2.4 Vppd of PAM-4 output swing, the highest AMUX FoM is obtained. To the best of the authors' knowledge, these are the highest performances reported to date for an AMUX(driver). Additionally, an AMUX-driver chip is assembled with a TFLN modulator, demonstrating an E/O bandwidth in excess of 85 GHz, while supporting the generation of 100-GBd PAM-4 optical signals, without DSP or active cooling.

Vertical silicon nanowire transistors are among the most promising device concepts for future low-power electronics due to their gate-all-around nature as well as their 3D stacking potential. In this work we review the current status of transistor fabrication on vertical silicon nanostructures and identify the most important challenges for successful process integration. Channel patterning, source/drain contact formation, gate-deposition and spacer engineering are identified as key steps independent on the actual process integration sequence. We conclude the paper with two emerging device examples and discuss the influence of the processing challenges on the transistor design.

This article presents a new methodology to accurately characterize indium phosphide (InP) bipolar transistors up to 500 GHz. Following design optimization of RF test structures specifically developed for the on-wafer thru-reflect-line (TRL) calibration technique, InP/GaAsSb double heterojunction bipolar transistors have been successfully characterized up to 500 GHz. Moreover, the high current model (HICUM) compact model was validated against measurements for different operating conditions and various geometries for the first time up to 500 GHz. The physics-based compact model and the associated scalable parameter extraction flow allowed us to demonstrate the scalability of this terahertz (THz) InP double heterojunction transistor (DHBT) technology, offering possibilities for further design-level explorations. State-of-the-art cut-off frequencies of this THz transistor technology featuring f(MAX) reaching 1 THz for transistor geometries with 0.15- mu m emitter widths were experimentally verified and confirmed by the compact model predictions.

This work introduces SENSOTERIC, a multi-partner project that aims at leveraging the properties of emerging Reconfigurable Field Effect Transistors (RFETs) to develop a sensor platform. RFETs will be used for a generic sensor interface and for a dedicated transducer element. In the first case, our goal is to develop an analog front-end interface that can be tuned at runtime to adapt to different environmental conditions and be used in a broad spectrum of applications. This feature shall be enabled by the polarity-control and negative differential resistance characteristics of the reconfigurable devices employed, that are co-integrable on industrial CMOS processes such as 22 nm FDSOI. In the second case, we want to exploit the intrinsic nature of these doping-free devices to yield better 1/f noise performances when compared to classic CMOS transducers. Moreover, the presence of un-gated areas on top of the channel of these devices makes them the perfect candidates to be functionalized. In this early-stage overview of the project, we will introduce the key features and the vision that make SENSOTERIC a unique contribution towards smart sensing solutions in environmental monitoring and healthcare.

Addressing temperature hot-spots resulting from self-heating effects (SHE) poses a significant challenge in the design of emerging nanoscale transistors, such as vertical junctionless nanowire field-effect transistors (VNWFETs), due to reduced thermal conductivity. Consequently, electrothermal modeling becomes crucial for a comprehensive understanding of the underlying physical mechanisms governing carrier degradation and thermal conduction in these nanoscale devices. In this study, we present an enhanced drift-diffusion model coupled with nonlocal Guyer-Krumhansl equations to accurately capture carrier-phonon interactions and explore the electrothermal characteristics of gate-all-around (GAA) VNWFETs. Pulsed current-voltage (I-V) measurements are employed to investigate the performance of a state-of-the-art 18 nm VNWFET technology. Furthermore, we report on the influences of both trapping and SHE under high-bias conditions for varying pulse widths. Our findings reveal that optimization of mobility degradation mechanisms allows for improved control over the physical behavior of carrier transport in these emerging technologies. Through careful consideration of these factors, it becomes possible to enhance the overall performance of GAA VNWFETs, particularly in mitigating temperature hot-spots and addressing challenges associated with SHEs.

With the continuous increase in data traffic and enormous consumption of data in terms of video on demand services and cloud computing, there is an increasing demand for high speed and high sensitivity short reach receivers for passive optical networks (PON) access network which are point to multi‐point networks. Avalanche photodiodes (APD) are the standard receivers in PON networks due to their high sensitivity and low cost. However, it is currently not clear if they can provide high bandwidth above 40 GHz with good performance (gain, noise, etc.). Furthermore, standard PIN photodiodes do not provide sufficient sensitivity for PON networks. Therefore, in this article a SOA‐UTC receiver is proposed, which is a photonic integrated circuit (PIC) comprising a semiconductor optical amplifier (SOA) for optical preamplification and a high‐speed uni‐travelling‐carrier (UTC) photodiode for opto‐electronic conversion. A very high responsivity of 140 A W −1 is demonstrated, with a polarization dependent loss (PDL) around 1 dB and a 3 dB bandwidth of 48 GHz, which is very promising for future PON network with 50 Gbit s −1 capacity and above.

This multi-partner-project contribution introduces the midway results of the Horizon 2020 FVLLMONTI project. In this project we develop a new and ultra-efficient class of ANN accelerators, the neural network compute cube ((NC2)-C-2), which is specifically designed to execute complex machine learning tasks in a 3D technology, in order to provide the high computing power and ultra-high efficiency needed for future edgeAI applications. We showcase its effectiveness by targeting the challenging class of Transformer ANNs, tailored for Automatic Speech Recognition and Machine Translation, the two fundamental components of speech-to-speech translation. To gain the full benefit of the accelerator design, we develop disruptive vertical transistor technologies and execute design-technology-co-optimization (DTCO) loops from single device, to cell and compute cube level. Further, a hardware-software-co-optimization is executed, e.g. by compressing the executed speech recognition and translation models for energy efficient executing without substantial loss in precision.

In this work, we present the first small signal characterization of a reconfigurable field effect transistor. The device under test is a back-bias RFET integrated into an industrial 22nm FDSOI platform. These devices are particularly interesting for CMOS co-design as they enable a frequency doubling functionality using a single transistor, without the need for inductive elements. Extraction of figures of merit and a comprehensive small signal analysis are performed. It is demonstrated that an ambipolar back-bias reconfigurable field-effect transistor can be modelled using a conventional small-signal equivalent circuit. This shows promise for modelling engineers and circuit designers to explore innovative applications of this new emerging technology.

In this paper, we present the fabrication, characterization, and electromagnetic simulation of open pad test structures on silicon-on-insulator substrates, with an emphasis on the impact of the substrate properties on RF performance. Targeting the design of optimal RF test structures for emerging technologies, we demonstrated that a high-resistivity substrate is essential to minimize losses and parasitic capacitances in RF measurements for technologies using silicon-on-insulator wafers.

This work presents new insights into 3-D logic circuit design with vertical junctionless nanowire FETs (VNWFET) accounting for underlying electrothermal phenomena. Aided by the understanding of the nanoscale heat transport in VNWFETs through multiphysics simulations, the SPICE-compatible compact model captures temperature and trapping effects principally through a shift of the device threshold voltage. Circuit-level simulations indicate a strong impact of temperature variation on functionality and figures of merits, such as energy-delay products. Subsequent guidelines for design considerations are discussed that are intended to provide feedback for technology improvements.

InP double heterojunction bipolar transistors (InP DHBTs) are one of the key technologies considered for terahertz (THz) applications. The improvement of their frequency performance is challenging and strongly dependent on various parameters (manufacturing process, geometry, and epitaxial structure). In this article, a novel method is developed to take into account these parameters and predict the frequency performance of the technology. This approach consists of rebuilding the S-parameter matrix of the small-signal model. Elements of the small signal model are identified, and their assessment is described in detail. Once calibrated with the present state-of-the-art device features, the model shows a good agreement with the measurements. Based on this result, analysis of the emitter and base technological features are performed along with optimizations of the vertical structure. Finally, the necessary optimizations for developing a THz transistor are detailed. This works provides guidelines for technological improvement and opens the way for designing transistors operating at frequencies above a THz.

In this article, we present the first detailed experimental study of electrothermal effects in 3-D vertical gate-all-around (GAA) junctionless nanowire transistors (JLNTs). In contrast with conventional CMOS technologies, JLNTs exhibit steady increase of current with temperature owing to weak mobility degradation in the highly doped nanowires. Consequently, in this work, we proposed novel experimental methods for extracting thermal resistance using dc and low-frequency (LF) S-parameter measurements. Experimental results obtained from different methods are validated against theoretical as well as simulated values obtained from multiphysics simulation of JLNTs.

Today, extensive research has focused on heat propagation in emerging nanoelectronic devices. With advances in the fabrication of nanowire (NW) transistors, thermal management has become a critical issue in cooling strategies and conducting materials. In this article, we present a novel multiphysics analysis of the nanoscale thermal transport in 18-nm vertical junctionless gate-all-around (GAA) silicon NW transistors. Based on this multiphysics analysis, we developed a new computational model derived from the Guyer–Krumhansl equation (GKE) for describing heat transport within the nanoscale device. Our simulations results agree well with available theoretical approaches as well as measurement data.

This article reports the first accurate and physics-based Verilog-A implementation of the fully analytic form of photocurrent in SPICE compact models for uni-traveling carrier (UTC) photodiodes (PDs). To overcome the limitations of single-pole network implementations for modeling frequency dependence of the photo-response, especially at frequencies beyond 100 GHz, we explored different solutions for the complete analytic equation of the dynamic photocurrent. A new implementation has been proposed which requires three additional nodes in the UTC-PD electrical equivalent circuit and offers the best tradeoff between accuracy and computational efficiency. Model validation has been performed against on-wafer measurements from two UTC-PD technologies depicting very good accuracy over the entire frequency range.

In this paper, we perform on-wafer characterization of an InP double heterojunction bipolar (InP DHBT) up to 220 GHz using conventional characterization and de-embedding methods. Transistor measurements are analyzed through a comparison with the small-signal model simulation. Transistor accesses are modeled in order to understand how parasitic parameters are distributed and to propose subsequent improvements.

Understanding trap dynamics and formation of localized temperature hot-spots due to self-heating is crucial for the design optimization of emerging vertical junctionless nanowire transistors (VNWFET). This work investigates the operation of an 18 nm VNWFET technology, for the first time, leveraging pulsed current-voltage measurements. Results indicate increased trap activity as well as electrothermal effects with increasing pulse width. Multiphysics simulations are then used to provide a deeper insight into the nanoscale transport of the VNWFETs. We then incorporated these effects into the SPICE-compatible VNWFET compact model and further investigated the behaviors of trapping and electrothermal effects in basic logic circuits based on the compact model simulation.

This work presents a comprehensive analysis of electrothermal effects in emerging 3D vertical junctionless nanowire transistors (VNWFETs) using on-wafer measurements under a wide range of temperature and validated against numerical and compact model simulations. Experimental observations indicate an increase of the drain current with the temperature, conforming to the behavior of junctionless FETs. Multiphysics simulations reveal formation of temperature hot-spots that adversely affect thermal conductivity in smaller geometries. The VNWFET compact model was then modified to account for the underlying electro-thermal effects as well as dynamic self-heating. Model simulations and the experimental results at different measurement temperatures for different transistor geometries show good agreement. The developed SPICE-compatible compact model was then used for studying the impact of electrothermal effects on the performances of basic 3D logic circuits.