The method of using CVD or Chemical Vapor Deposition [1-2] in the formation of graphene synthesis has recently progress quite a lot. The material shows exceptional electronic properties and also characterizes suspended graphene resonators. But the fabrication of this material involves the transfer of graphene from its copper catalyst to the required substrate using wet chemical etching method. This transfer procedure introduces metal residues, wrinkles and holes in the graphene. These issues are necessary to be dealt with and hence provide the need for a transfer-free fabrication method for suspended graphene, using CVD method. In this paper we fabricate suspended graphene without the use for any transfer technique. It can be grown both using a catalyst like thin copper films, and non-catalyst like directly on a dielectric substrate. Such a fabrication procedure includes the growth of graphene by CVD followed by the deposition of Au/Ti electrodes defined by e-beam lithography (ebl). Later on there will be graphene etching using oxygen plasma. The structures in the end are made suspended by chemically etching the substrate layer at the top and later on dried.

This article introduces a silicon carbide (SiC)-based high-voltage silicon-controlled rectifier (HV-SCR) for on-chip electrostatic discharge (ESD) protection. The SiC HV-SCR is formed by implanting a $\text{p}^{+}$ region into the n-well of SiC laterally diffused metal-oxide semiconductor (LDMOS) structures. Both LDMOS and HV-SCR structures were characterized using a transmission line pulse (TLP) system to investigate their ESD behaviors. The TLP measurement results show that the trigger voltage ( ${V}_{\text {t1}}$ ) of the SiC HV-SCR is $\sim 230$ V and has minor dependence on the drift length. The ${V}_{\text {t1}}$ value of the SiC LDMOS decreases from 224 to 202 V when its drift length decreases from 6 to 4 $\mu \text{m}$ . TLP measurements with 500- $\Omega $ impedance were conducted to obtain an accurate holding voltage ( ${V}_{\text {h}}$ ) and failure current ( ${I}_{\text {t2}}$ ) of HV-SCR and LDMOS. Relatively high ${I}_{\text {t2}}$ (i.e., 33 mA/ $\mu \text{m}$ ) of the HV-SCR structure was observed, which is much stronger than the LDMOS structure (i.e., 0.2 mA/ $\mu \text{m}$ ). The ${V}_{\text {t1}}$ and ${V}_{\text {h}}$ values of HV-SCR were also investigated with varying gate bias voltages. Moreover, technology computer-aided design (TCAD) simulations of the SiC HV-SCR and LDMOS were carried out to further understand their ESD behaviors.

In this paper, we report a wind energy harvesting system for Internet of Things (IoT)-based environment monitoring (e.g., temperature and humidity, etc.) for potential agricultural applications. A wind-driven electromagnetic energy harvester using rotational magnet pole-pairs (rotor) with a back-iron shield was designed, analyzed, fabricated, and characterized. Our analysis (via finite element method magnetic simulations) shows that a back-iron shield enhances the magnetic flux density on the front side of a rotor where the series connected coils interact and convert the captured mechanical energy (wind energy) into electrical energy by means of electromagnetic induction. A prototype energy harvester was fabricated and tested under various wind speeds. A custom power management circuit was also designed, manufactured, and successfully implemented in real-time environmental monitoring. The experimental results show that the harvester can generate a maximum average power of 1.02 mW and maximum power efficiency of 73% (with power management circuit) while operated at 4.5 m/s wind speed. The system-level demonstration shows that this wind-driven energy harvesting system is capable of powering a commercial wireless sensor that transmits temperature and humidity data to a smartphone for more than 200 min after charging its battery for only 10 min. The experimental results indicate that the proposed wind-driven energy harvesting system can potentially be implemented in energetically autonomous IoT for smart agriculture applications.

This paper describes the negative charge pump design in state-of-the-art SiC BJT technology along with its assembly on the LTCC module for extremely high-temperature applications. Kiln thermal oven is used to test the system at 500°C and evaluate the system's high-temperature performance. The charge pump design is separated into two sections: a diode-connected BJT charge pump and a cross-coupled RC oscillator. Commercially available NHT dielectric capacitors (390 pF) are used for both circuit sections. The designed LTCC module used DuPont™ 9k7 dielectric with gold metallization for routing traces. The oscillator output frequency varied from 35.7 kHz to 125 kHz across temperature for a fixed supply voltage of 11 V.

To equip farmers with tools that aid in crop monitoring and help optimize the use of valuable resources such as fertilizer and water, a wireless sensor node is developed. The sensor node communicates extracted data from inside the crop pertaining to the plant's health to an end user. A transmitter and receiver are the key electronics in effective wireless communications between the sensor node and end user. Several RF circuits were designed and fabricated in GlobalFoundries' (GF) 0.13 μm BiCMOS process and combined with a commercial off-the-shelf wake-up receiver to enable data transmission upon user request. This low power prototype design is intended to be supplied from a micro-battery with a capacity of 278.6 Joules and proposed lifetime of 1 month. The integrated circuits designed include an RF power amplifier, bandgap reference and linear regulators for power supply management.

In this paper, the design and implementation of a gate driver in SiC CMOS process is presented for heterogeneous integration (HI) inside the commercial SiC power module. The output stage of the gate driver circuit includes four-pull up (QP 1,2,3,4) and four-pull down (QN 1,2,3,4) transistors to vary current drive strength. The output stages are driven by tri-state buffer chains that are controlled by comparator based control circuits. The driver is tested over temperature up to 300°C. At higher temperatures, the peak drive current (under full strength with no external load) increases with the output swing remaining the same. Variation of the driver’s output pull-up and pull-down stage at higher load capacitance is also discussed in this paper. The driver circuit layout is optimized to utilize the maximum die area allowed by the process. The gate driver layout is 4.8mm × 4.8mm. The bond pads and layout orientation are configured for flip-chip packaging but can also be used for wire-bonding.

This paper establishes the first integrated silicon carbide (SiC) CMOS linear voltage regulator. The design provides for a continuous load current exceeding 100 mA and a 15 V output from an input voltage of 20 to 30 V. The foundation of the regulator's feedback loop is formed by a two-stage SiC operational amplifier. Both internal and external passive components are used in the frequency compensation network. An external 7.5 V supply is connected to the operational amplifier and acts as the reference voltage. At 400 degrees C, experimental results show a line regulation of better than 1.5 mV/V under a 100-mA load. The load regulation with a 30-V input and at 400 degrees C is shown to be 0.42 mV/mA. Sustained operation of the linear regulator is demonstrated over 30 h at 300 degrees C.

This paper presents functional hightemperature analog circuits in silicon carbide bipolar technology. The circuits will collectively form the analog signal conditioning block for a wireless telemetry system in an extreme environment (above 400 degrees C). The signal conditioningblock is composed of a lowdc gain operational amplifier, a negative voltage charge pump (CP), an RC oscillator, and a voltage regulator. The circuits are tested up to 450 degrees C. The measured open-loop gain for the amplifier at 450 degrees C is 30 dB. The regulator provides approximately 9-V output at 450 degrees C for a fixed load current of up to 18 mA and an applied reference of 4.5 V. The negative voltage CP requires an oscillating signal at its input, which is provided by the RC cross-coupled oscillator. The CP provides about -5 V at 450 degrees C.

A variable drive strength gate driver for gallium nitride (GaN) power FETs intended for a 6.6 kW EV charger is presented. The driver incorporates low-side and high-side channels in a single integrated circuit that is flip-chip capable. The gate driver has been designed in a 0.18 μm silicon-on-insulator (SOI) process featuring deep trench isolation, 1.8 V and 5 V CMOS devices, and DMOS devices rated up to 200 V. The on-chip protection circuitry includes an undervoltage lockout (UVLO) in both channels, desaturation detection, and a VDS sensing circuit for the low-side power FET. The novel VDS sensing implementation enables the gate driver to have a dynamically controlled source current, programmable between 0.15 A and 2.4 A, to mitigate excessive ringing. Both low and high-side channels have a sink current of 5 A. The gate driver IC also includes active Miller clamping, a low-side to high-side level shifter, and a power supply for each channel.

Abstract Electronic systems capable of withstanding high temperature environments are in high demand in various applications such as logging-while-drilling (LWD) systems and embedded electronics which are in the core of gas turbine engine controls. Designing memory that can process massive amounts of data in harsh environments while consuming low power opens doors for next generation, smart, high temperature electronic systems. In this work, a CMOS based six transistor (6T) static random-access memory (SRAM) cell is designed and implemented in a state-of-the-art SiC 1μm triple well CMOS process. The designed SiC SRAM cell performance has been characterized for different values of cell ratios (CR) [0.5, 0.6, 1, 1.5, 2, 2.5] and pull-up ratios (PR) [1, 2, 3, 4, 5, 6] to determine the cell size with optimal performance parameters. Static noise margin (SNM) values for the different combinations of CR and PR are calculated using the model developed by Seevinck, et. al. [13]. The highest SNM values observed at 25°C and 300°C are 4.71 V and 4.65 V, respectively. Read static noise margin (RSNM) values of 1.94 V and 1.90 V are achieved at 25°C and 300°C, respectively. Analysis of measured data shows that the optimum cell size is with a CR of 2.5 and a PR of 6. However, these results are significantly impacted by highly resistive ohmic contacts.

In order to develop electrostatic discharge (ESD) protection structures in Silicon Carbide (SiC) process, the ESD properties of SiC silicon-controlled rectifier (SCR), lateral-diffused MOS (LDMOS) and NMOS devices are reported in this paper. All devices were fabricated using Fraunhofer 4H-SiC Bipolar-CMOS-DMOS (BCD) process and characterized by transmission line pulse (TLP) system. The scalability of the failure current (I t2 ) of NMOS with multiple fingers is reported. The critical parameters (i.e. gate length and drift region) of LDMOS are varied to understand the effects on the triggering voltage and other ESD characteristics of the devices. The comparison of the I t2 between high voltage SCR (HV-SCR) and LDMOS has been investigated. TLP results show that HV-SCR structures have much higher I t2 than LDMOS structures. Cost-effective ESD protection structures can be designed by these HV-SCR devices. Furthermore, ESD characteristics of SiC HV-SCR and NMOS structures are simulated using Silvaco technology computer-aided design (TCAD) software.

This paper describes a silicon carbide (SiC) Bipolar-CMOS-DMOS (BCD) process technology and presents the corresponding characterization results. The process enables the design of integrated circuits (ICs) capable of high temperature operation and heterogeneous integration into SiC power modules. The paper showcases the cross-section of the triple-well, single metal layer SiC BCD process and details the key process challenges. Characterization results for NMOS, PMOS, LDMOS, and BJT structures are presented. DC output characteristics of the standard 1.5 μm NMOS and PMOS are shown for temperatures of 25°C and 300°C. The drain-to-source breakdown voltages observed for the LDMOS (at 1 nA leakage) is 178 V at 25°C. The integrated passives available in the process include N-diffusion resistors with a sheet resistance of approximately 1.2 kΩ/□ and poly-to-N-diffusion capacitors with 0.612 fF/μm2 capacitance.

The paper presents a comprehensive investigation of the key differences between the characteristics of Si and SiC low-voltage (LV) BJT. The purpose of this investigation is to identify the special characteristics of SiC LV BJT which will require changes in the parameter extraction sequence of the conventional compact models. Characteristics of LV SiC bipolar devices fabricated in KTH's ion-implantation-free process are compared with a similar Si BJT characteristics. The investigation proves that key differences arrive from the low intrinsic carrier concentration, high contact resistance, and the presence of interfacial trap states in the SiO 2 /SiC interface. To verify the claims, TCAD deck for LV SiC bipolar device has been developed. TCAD simulation results clearly indicate the importance of interface trap states and, comparatively, large internal resistance in the base region. It also verifies the very low current of SiC BJT at the operating voltage range of Si BJT, which is difficult to measure with curve tracers.

This paper presents an 8-b digital to analog converter (DAC) and 8-b analog to digital converter (ADC) for high-temperature applications. The pair of data converters were designed in a 1.2-(-)m silicon carbide CMOS process and have been tested from 25 degrees C to 400 degrees C. At 400 degrees C, the DAC has a maximum differential nonlinearity (DNL) and integral nonlinearity (INL) error of 1.2 least significant bit (LSB) and 2.7 LSB, respectively, while the offset and the gain error are 5.9 and 2.7 LSB. The ADC has a maximum DNL and INL error of 3.6 and -3 LSB, respectively, while the offset error is -7 LSB and the gain error is 2.6 LSB. The ADC has an SNDR = 32.15 dB and effective number of bits = 5.05 b at 300 degrees C. The DAC is the first of its kind in silicon carbide CMOS, while the ADC is the first reported at temperatures over 300 degrees C.

This paper describes a silicon carbide pulse width modulation (PWM) signal generator in the 1.2 μm HiTSiC CMOS process developed by Raytheon Systems Ltd. The design features a 6-b binary input, which allows for setting a system's duty cycle. The results presented in this paper utilize a field programmable gate array board in the test setup to dynamically set the duty cycle by controlling each bit. A control current is also available to give the user added flexibility for tuning the duty cycle. Experimental results show the duty cycle range of the PWM generator to be between 4.7% and 95.2% at 400 °C. Sustained operation of the circuit is demonstrated over a period of 50 h at 300 °C. Finally, the PWM generator is evaluated in the operation of a boost converter.

This paper describes the design of a SiC pulse width modulation (PWM) signal generator in the HiTSiC ® CMOS process from Raytheon Systems Limited. The high-temperature applications of the circuit include motor control in heavy equipment, deep earth drilling, dc-dc voltage converters and power inverters. The results presented in this paper are for the PWM circuit operating with an input clock frequency of 100 kHz and a supply voltage range of 12 to 15 V. The building blocks for the PWM include a current-starved delay generator, a comparator and XNOR gates. The delay is controlled by a 6-bit binary input that allows the user to dynamically tune the duty cycle. Experimental results show the circuit to have a tunable duty cycle between 16.3% and 84.3% at 400°C.

This paper describes a high temperature voltage comparator and an operational amplifier (op-amp) in a 1.2-μm silicon carbide (SiC) CMOS process. These circuits are used as building blocks for designing a high-temperature SiC low-side over current protection circuit. The over current protection circuit is used in the protection circuitry of a SiC FET gate driver in power converter applications. The op-amp and the comparator have been tested at 400 °C and 550 °C temperature, respectively. The op-amp has an input common-mode range of 0-11.2 V, a dc gain of 60 dB, a unity gain bandwidth of 2.3 MHz, and a phase margin of 48° at 400 °C. The comparator has a rise time and a fall time of 38 and 24 ns, respectively, at 550 °C. The over current protection circuit, implemented with these analog building blocks, is designed to sense a voltage across a sense resistor up to 0.5 V.

The paper presents performance analysis of an analog front end (AFE) for body-coupled communication (BCC) which is based on data transmission via capacitive coupling through the human body. The AFE designs by cascading differential preamplifier and Schmitt trigger. A flipped voltage follower (FVF) topology is used as part of the preamplifier design. The operation frequency of the overall system is mentioned as 10 MHz. The open loop gain is 24.01 dB and the close loop gain is 19.43 dB for this preamplifier. The input referred noise PSD is 8.69 nV/√Hz at 10 MHz. The system runs on a supply voltage of 1 V with implementation being done on 65 nm CMOS technology.

This paper presents a newly cascaded voltage mode tri-state driver circuit for body-coupled communication (BCC) designed in 65 nm CMOS technology. Each stage of the driver circuit has been resized to meet the requirement of the BCC. It has a driving capability of 6 mA from 1.2 V supply with 10 MHz operating frequency. Different analysis has been performed to get the optimum results for the proposed circuit. The analysis shows cycle to cycle jitter to be less than one and power supply rejection ratio (PSRR) 65 dB, indicating the good emission of supply noise. In addition, the driver circuit does not require a filter to emit the noise because the body acts like a low pass filter.

In order to achieve the desired ride comfort, road handling performance and to solve the uncertainties, a new modified skyhook control strategy with adaptive gain that dictates the vehicle's semi-active suspension system has to be presented. Recent works do not consider the effect of road bank angle or the dynamic model of the tilting standard passenger vehicles. The lack of incorporating road bank angle creates a non-zero steady state torque requirement. The paper addresses these issues. The paper introduces a proposed skyhook control system (SKDT) along with direct tilt control which demonstrates that the integrated suspension control strategy can be used to tilt a vehicle inward to act against the lateral acceleration due to steering maneuvers. The designed SKDT system was observed to improve the isolation of the vibration and handling performance and stabilize the tilt mode of the system by keeping the vehicle stable and safe from rollover.