In this paper, a cost efficient test methodology to screen chips that have resistive open defects under the presence of process variation is proposed. The proposed test methodology is based on small delay defect testing. The entire test session is divided into several subsessions. In each subsession, test patterns are applied with a different frequency of test clock, all of which are faster than the rated clock. Unlike others, different test patterns are generated and applied in each subsession to reduce test application time. A simple three step screening method is also proposed. The first step identifies scan outputs that can fail only if there are defects under the possible worst case process variation. In the second step, we assume that a chip failed due to a defect if the number of faulty scan outputs in a test pattern is much larger than that of faulty scan outputs of a typical defect free chip. Finally, the third step screens defective chips by comparing the number of fail patterns. Among 10 benchmark circuits used for the experiments, the proposed method was able to screen successfully more than 90% of defective chips for 8 circuits.

This work is the summary of improvements in processing capability implemented and tested on the LITHIUS Pro (TM) -i / TWINSCAN (TM) XT:1950Hi litho cluster installed at ASML's development clean room at Veldhoven, the Netherlands. Process performance with regards to CD uniformity (CDU) and defectivity are investigated to confirm adherence to ITRS roadmaps specifications(1). Specifically, imaging capabilities are tested for 40nm line 80nm pitch with the new bake plate hardware for below hp 3Xnm generation. For defectivity, the combination of Coater/Developer defect reduction hardware with the novel immersion hood design will be tested.For CDU improvements, the enhanced Post Exposure Bake (PEB) plate hardware was verified versus performance of the previous technology plate. Additionally, after the PEB improvement, a remaining across wafer signature was reduced with an optimized develop process. The total CDU budget was analyzed and compared to previous results. Finally the optimized process was applied to a non top coat resist process. For defectivity improvements, the effectiveness of ASML's new immersion hood and TEL's defect reduction hardware were evaluated. The new immersion hood performance was optimal on very hydrophobic materials, which requires optimization of the track hardware and process. The high contact angle materials could be shown to be successfully processed by using TEL's Advanced Defect Reduction (ADR) for residues related to the high contact angle and optimized bevel cut strategy with new bevel rinse hardware. Finally all the optimized processes were combined to obtain defect counts on a highly hydrophobic resist well within manufacturing specifications.

Test pattern generation is an important part of the VLSI testing flow that offers many possibilities that can be explored for reducing test power dissipation. The issue of test power reduction can be addressed at various stages of test generation for logic circuits, by employing low-power automatic test pattern generation. low-power test compaction, low-power X-filling, and low-power test vector ordering. In addition, power dissipation in memory testing can be reduced through low-power memory test generation. The most significant advantage of reducing test power through low-power test generation is that this approach causes neither circuit overhead nor performance degradation. However, low-power test generation is a complex technical field, in which many important factors in addition to the effect of test power reduction such as test vector count inflation, potential fault coverage loss, test generation time increase, compatibility with compressed scan testing, and test generation flow modification should be taken into careful consideration. Therefore, the objective of this chapter is to provide a comprehensive overview of the basic principals and fundamental approaches to low-power test generation, along with detailed descriptions of typical methods, so as to help researchers devise more innovative solutions and practitioners build better flows in order to achieve the goal of optimally reducing test power through low-power test generation.

A self-diagnosis circuit that can be used for built-in self-repair is proposed. The circuit under diagnosis is assumed to be composed of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defective. Since the proposed self-diagnosis circuit is implemented on the chip, responses that are scanned out of scan chains are compressed by the group compactor, the space compression circuit, and finally, the time compression circuit to reduce the volume of test response data. Both the space and time compression circuits implement a Reed-Solomon code. Unlike prior work, in the proposed technique, responses of all FRUs are observed at the same time to reduce diagnosis time. The proposed diagnosis circuit can locate up to l defective FRUs. We propose a novel space compression circuit that reduces hardware overhead by exploiting the frequency difference of the scan shift clock and the system clock and by combining scan cells into groups of size r. When the size of constituent multiple-input signature register (MISR) is m, the total number of signatures to be stored for the fault-free signature is 2 lmB bits, where 1≤ B ≤ m. The experimental results show that the proposed diagnosis circuit that can locate up to four defective FRUs in the same test session can be implemented with less than one percent of hardware overhead for a large industrial design. Hardware overhead for the diagnosis circuit is lower for large CUDs.

In this paper a novel diagnosis method is proposed. The proposed technique uses machine learning techniques instead of traditional cause-effect and/or effect-cause analysis. The proposed technique has several advantages over traditional diagnosis methods, especially for volume diagnosis. In the proposed method, since the time consuming diagnosis process is reduced to merely evaluating several decision functions, run time complexity is much lower than traditional diagnosis methods. The proposed technique can provide not only high resolution diagnosis but also statistical data by classifying defective chips according to locations of their defects. Even with highly compressed output responses, the proposed diagnosis technique can correctly locate defect locations for most defective chips. The proposed technique correctly located defects for more than 90% (86%) defective chips at 50x (100x) output compaction. Run time for diagnosing a single simulated defect chip was only tens of milli-seconds.

This paper presents a test data compression scheme that can be used to further improve compressions achieved by linear-feedback shift register (LFSR) reseeding. The proposed compression technique can be implemented with very low hardware overhead. The test data to be stored in the automatic test equipment (ATE) memory are much smaller than that for previously published schemes, and the number of test patterns that need to be generated is smaller than other weighted random pattern testing schemes. The proposed technique can be extended to generate test patterns that achieve high n-detection fault coverage. This technique compresses a regular 1-detection test cube set instead of an n-detection test cube set, which is typically n times larger. Hence, the volume of compressed test data for n-detection test is comparable to that for 1-detection test. Experimental results on a large industry design show that over 1600X compression is achievable by the proposed scheme with the test sequence length, which is comparable to that of highly compacted deterministic patterns. Experimental results on n-detection test show that test patterns generated by the proposed decompressor can achieve very high 5-detection stuck-at fault coverage and high compression for large benchmark circuits.

A self-diagnosis circuit that can be used for builtin self-repair is proposed. The circuit under diagnosis is assumed to be comprised of a large number of field repairable units (FRUs), which can be replaced with spares when they are found to be defective. Since the proposed self-diagnosis circuit is implemented on the chip, responses that are scanned out of scan chains are compressed first by the space compression circuit and then by the time compression circuit to reduce the volume of test response data. Both the space and the time compression circuit implement a Reed-Solomon code. Unlike prior work, in the proposed technique, responses of all FRUs are observed at the same time to reduce diagnosis time. The proposed diagnosis circuit can locate up to l defective FRUs. We propose a novel space-compression circuit that reduces hardware overhead by exploiting the frequency difference of the scan shift clock and the system clock. When the size of constituent multiple-input signature-register (MISR) is m, the total number of signatures to be stored for the fault-free signature is 2lmB bits, where 1 les B les m. The experimental results show that the proposed diagnosis circuit that can locate up to 4 defective FRUs in the same test session can be implemented with less than 1% of hardware overhead for a large industrial design. Hardware overhead for the diagnosis circuit is lower for large CUDs.

We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes.

This paper presents a new blocking logic to block unknowns for temporal compactors. The proposed blocking logic can reduce data volume required to control the blocking logic and also increase the number of scan cells that are observed by the temporal compactors. Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. In this paper, the blocking logic gates for some groups of scan chains that do not capture unknowns are bypassed. Since all the scan cells in these scan chain groups are observed without specifying the corresponding bits in control patterns, fewer specified bits are required and more scan cells are observed. The seed size is further reduced by reducing numbers of specified bits in the densely specified control patterns. The proposed method can always achieve the same fault coverage that can be achieved by direct observation of scan chains. Experiments with large industrial designs clearly demonstrate that the proposed method is scalable to large circuits. Hardware overhead for the proposed blocking logic is very low.

This paper presents a scan-based DFT technique that uses limited number of enhanced scan cells to reduce volume of delay test patterns and improve delay fault coverage. The proposed method controls a small number of enhanced scan cells by the skewed-load approach and the rest of scan cells by the broadside approach. Inserting enhanced scan cells reduces test data volume and ATPG run time and improves delay fault coverage. Hardware overhead for the proposed method is very low. The scan inputs where enhanced scan cells are inserted are selected by gain functions, which consist of controllability costs and usefulness measures. A regular ATPG can be used to generate transition delay test patterns for the proposed method. Experimental results show that test data volume is reduced by up to 65% and fault coverage is improved by up to about 6%.

This paper presents techniques to improve compressions by improving fault coverage that can be achieved by broadcast scan. Due to reconvergent gates that artificially occur in broadcast scan, broadcast scan fault coverage is often much lower than standard serial scan fault coverage. The proposed scan chain reordering technique improves broadcast scan fault coverage by minimizing the number of reconvergent gates and hence no or very small number of test patterns are required to be applied by standard serial scan to detect faults undetected by broadcast scan. This increases the overall compression ratio. To eliminate or minimize increase in routing overhead, the distance that each scan cell can be relocated by the scan chain reordering procedure is limited. Test points are inserted to further reduce correlation among outputs of scancells. The proposed scan chain reordering technique improved broadcast scan fault converge by up to 8.5%. Large fault coverage improvement was achieved by the proposed method, especially for circuits that suffer low broadcast scan fault coverage. Broadcast scan fault coverage for the largest two industrial designs was even higher than standard serial scan fault coverage.

This paper presents an efficient method to block unknown values for temporal compactors. The control signals for the blocking logic are generated by a linear feedback shift register (LFSR). Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. The size of the control LFSR, which is determined by the number of specified bits in the most specified control pattern, is minimized by propagating only one fault effect for each fault and targeting the faults that are uniquely detected by each test pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Very high compression (over 230X) is achieved for benchmark and industrial circuits by the proposed method. Experimental results show that the sizes of control data for the proposed method are smaller than prior work and the runtime of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low.