In this article, we have addressed an important issue called ambipolarity in electrically doped tunnel field effect transistors, which greatly hinders its use in circuit applications. We introduced asymmetric biasing in polarity gates 1 and 2 of the electrically doped TFET. Polarity gate 2 has a fixed bias of -1.2 V and polarity gate 1 is provided with a variable bias of +1.2 V, +1.0 V, and +0 .8V. The asymmetric bias in both polarity gates introduces asymmetric doping in the source and drain regions, which introduces a wider tunneling width in the drain-channel region and prevents the tunneling of holes; hence, the ambipolar current is suppressed. The structure is studied in the thermal equilibrium, OFF, ON, and ambipolar states.

In this article, we explore a noteworthy aspect of Negative Capacitance FETs (NCFETs): the influence of transistor feature size on hysteresis behavior. The ferroelectric capacitance is directly proportional to the channel length, so as the transistor is scaled down, both the ferroelectric and MOS capacitances decrease. Our analysis shows that at a channel length of 16 nm, the ferroelectric capacitance falls below the MOS capacitance, resulting in the emergence of hysteresis in the device characteristics. Additionally, we investigate how scaling the transistor feature size impacts key phenomena such as negative Drain-Induced Barrier Lowering (DIBL), negative differential resistance (NDR), and the negative body effect coefficient. We also evaluate the performance of an NCFET-based inverter across different channel lengths and find that the device with a 22 nm channel length exhibits the lowest static and dynamic power dissipation among the cases studied.

Linearity and intermodulation distortion are very crucial parameters for RFICs design. Therefore, in this work, a detailed comparative analysis on linearity and intermodulation distortion of single metal (SMG) and double metal (DMG) double gate junction less transistor (JLT) is done using TCAD silvaco suite. Furthermore, the effects of temperature fluctuation, gate length variation, and gate material engineering on the linearity performance of both devices are also studied. A few significant figures of merit, including Voltage Intercept Point 2 (VIP2), Voltage Intercept Point 3 (VIP3), Third Order Intercept Power (IIP3), 1 dB Compression Point (P1dB), Third Order Intermodulation Distortion (IMD3), and the transconductance derivative parameters First Order Transconductance (gm1), Second Order Transconductance (gm2), and Third Order Transconductance (gm3) are used to assess the device linearity and intermodulation distortion of SMG and DMG JLT’s. The findings show that higher VIP2, VIP3, IIP3, 1-dB compression point and lower gm3, IMD3 values are obtained for the SMG JLT device when compared to its counterpart DMG JLT. SMG JLT, which assures strong linearity and low distortion.

In this article, we have studied passive voltage amplification in FE-FE-DE heterostructure. We have stacked two different ferroelectric oxides; one is second-order transition ferroelectric material (continuous transition ferroelectric material) and the other is first-order transition ferroelectric material (discontinuous transition ferroelectric material). Both ferroelectric materials have different polarities of anisotropy constant $(\beta)$ , which is tuned by varying the ferroelectric thickness and thus leads to its cancellation. The nullification of the anisotropy constant will reduce the non-linearity of the ferroelectric oxide and provide efficient matching between the ferroelectric and dielectric capacitance, which in turn delivers the higher voltage amplification in the heterostructure. Also, dynamic response and temperature analysis of heterostructure are studied further. It is observed that dielectric when added in series with the isolated ferroelectric capacitor the curie temperature shifts to a lower value.

Negative Capacitance Field Effect Transistors are well known for their superior performance over MOSFET and are a viable candidate to succeed the baseline FET in time ahead. We have studied the performance of 32 nm planar MOSFET with doped hafnium dioxide as a ferroelectric material. The functioning of the NCFET is entirely dependent on the equivalence between the ferroelectric and MOS capacitance. Our simulation results clearly indicated that the Sr doped HfO2 has close capacitance matching with MOS capacitance, when compared with other dopant material (Si, Al and Zr). This also reflects in the performance parameters (drain current and transconductance characteristics) of the device designed. Also, we have designed a resistive load inverter with doped hafnium dioxide, Sr doped among them has an edge over the other ferroelectric material in terms of noise margin and static power dissipation.

In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14 nm conventional FinFET to form NC-FinFET. Static and dynamic behavior of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET based SRAM, 6T-NCSRAM exhibits distinct behavior during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

To keep alive dimensional scaling, the never-ending progress of modern technology has sparked a plethora of exploratory computing and data storage studies. This has resulted in the search for new device structures, physical phenomena, and circuit topologies. Several device architectures such as tunnel FET, phase FET, and hybrid FET are being investigated to enable ultra-low-power circuit operation using sub-60 mV/decade (sub-kT/q) switching. These new exploratory devices have distinct potentials and constraints that must be thoroughly investigated before moving forward with their commercialization. One such device, 'negative capacitance-based FET,' has attained much attention in recent years due to its compatibility with the CMOS process and direct and indirect experimental evidence. The unique property in some ferroelectric/antiferroelectric oxide materials helps in keeping alive the dimensional scaling at lower technology nodes in NCFET. This chapter opens with a discussion of the material viewpoint, including the selection and optimization of an essential geometrical parameter, namely thickness in negative capacitance materials. The basic notions of negative capacitance's physical origin, stability, and history in attaining steep switching benefits in FETs are reviewed. Various modeling approaches, such as the major–minor hysteresis loop, multi-domain switching, and S-curve employing Landau, as well as the Prieasch model of negative capacitance, are explored. The advantages and disadvantages of various device architectures in the creation of NCFETs such as M-F-M-I-S and M-F-I-S for low-power applications are investigated. Finally, key NCFET features, such as DIBL and NDR, are discussed in order to achieve performance gains in low-power steep switching as well as memory applications.

In this paper, we have studied the effect of back gate bias technique in negative capacitance field effect transistor. In N-NCFET, OFF current decreases and threshold voltage increases with positive back gate bias, while with negative back gate bias, OFF current increases and threshold voltage decreases. This behavior of back gate bias in N-NCFET is quite different as compared to N-MOSFET. The primary reason behind this contradictory behavior is the dependence of internal node voltage (VMOS) on the body terminal of N-NCFET via bulk coupling factor. Further, we have utilized this property to design NCFET based inverter. Various figure of merits like noise margin, delay, static power dissipation and dynamic power dissipation is studied for the designed inverter. The designed inverter with suggested back gate bias shows 16% and 13.9% improved noise margin, and reduced delay performance respectively as compared to conventional NCFET without bias. Also, the power dissipation parameter (static and dynamic) is reduced by 90.1% and 3.8% respectively. We have also seen the effect of channel length scaling in the NCFET, decrement in the channel length improves the gate stack capacitance of NCFET which leads to decrement in OFF current at lower technology node.

The continued exploration of the ferroelectric-based negative capacitance field effect transistor (NCFET) for energy-efficient and higher current drivability merits has called for an investigation of the device compatibility for analog/RF applications. In this article, we assessed the analog/RF and linearity performance of NC-FinFET by employing high threshold voltage (HVT) techniques. Such techniques are essential to suppress the leakage current and improve the performance in scaled devices. Using well-calibrated TCAD models, we present insight into the advent of incorporating three different HVT approaches: 1) increase in the channel doping (N ch′ ), 2) drain underlap architecture (L dsu ), and 3) increase in the channel length (L g’ ) to investigate the analog/RF behavior. Further, various linearity figure-of-merits (FoMs) has been examined using g m2 , g m3 , VIP 2 , VIP 3 , IIP 3 , IMD 3 , and 1-dB compression point. We also varied N ch′ , L dsu , and L g’ to optimize the proposed HVT techniques for optimum performance. Moreover, the Gummel symmetry test, as a linearity measure, has been done for the optimized HVT-NCFinFET to investigate the drain current symmetry. Thus, the obtained results serve as a design guideline for adopting the NC-FinFET pertaining to low-power RF applications.

In the incessant search to overcome the power densities and energy efficient limitations, performance matrix of emerging electronic devices are being explored inevitably to find the alternatives of MOSFETs. We investigated and compared the delay and energy performance matrices of fin-shaped FET and negative capacitance FinFET (NC-FinFET) based devices and circuits designed on the same technology node. The improvement in the performance of NC-FinFET based CMOS circuits is enhanced due to the negative capacitance’s negative DIBL by employing a industry standard BSIM-CMG model. After analyzing at the device-level, detailed evaluation is carried out at logic level for embedded inverter chain, three-stage ring oscillators (ROs), and 2-bit ripple carry adders (RCA) for frequencies ranging between 10 kHz–1 GHz. Our findings revealed that the NC-FinFET based circuit has a lower delay for a given range of operating frequencies and saves a significant amount of power when compared to baseline FinFET, making NC-FinFET desirable for low power digital logic applications.

Abstract In this paper, a detailed evaluation of negative capacitance FinFET (NC-FinFET) based volatile static random access memory (6T-NCSRAM) is carried out by utilizing L-K equation for ferroelectric and calibrated BSIM-CMG model with 14nm conventional FinFET to form NC-FinFET. Static and dynamic behaviour of NC-FinFETs is explored and evaluated at different ferroelectric thickness. At supply voltage scaling, important SRAM performance metrics such as stability at different operation condition (hold, read and write mode) and standby leakage power were evaluated. When compared to traditional FinFET-based SRAM, 6T-NCSRAM exhibits distinct behaviour during low and high supply voltages. Moreover, the effect of wordline (WL) voltage pulse variation on 6T-NCSRAM is captured and minimum RC multiplier of 2RC is found to avoid functional failure of 6T-NCSRAM.

In this article, we have performed a comprehensive study into the Phase Transition Material based FinFET(PT-FinFET) device’s capabilities for low-power, energy-efficient applications through device circuit co-design perspective. Addressing its drawback at device and circuit level a novel device design known as the Negative Capacitance Phase Transition FinFET(NC-PTFinFET) is proposed by incorporating a ferroelectric material layer into the gate stack of the PTFinFET. The proposed device outperforms PTFinFET and FinFET in terms of SS and ON–OFF current ratio at the device level, as well as power and speed at the circuit level, and provides device tunability. With three case studies of embedded inverter chain, RO, and 2-bit RCA it was observed that the proposed NC-PTFinFET shows performance benefits in speed by reducing delay in these circuits with increasing NC thickness in comparison with the PTFinFET and FinFET. In contrast, increasing NC thickness in the proposed device energy efficiency is improved as compared to PTFinFET and FinFET.

An enormous study is being carried out in the field of emerging steep slope devices, specifically on negative-capacitance-based and phase transition-based devices. This article investigates the action of ferroelectric (FE) and phase transition material (PTM) on a hybrid device, negative-capacitance-assisted phase transition FinFET (NC-PT-FinFET). We encounter several unique phenomena resulting from this unified action and provide valid arguments based on these observations. A significant enhancement in the differential gain and transconductance, a unique variation in the effect of PTM on drain-channel coupling, tunability of hysteresis across PTM by FE thickness( [Formula: see text]), and ultralow subthreshold slope (SS) by lowering both of its factors are some of the major outcomes of the NC-PT-FinFET. Focus is built on comprehending the individual role of FE and PTM in the intriguing features observed in every device performance parameter with the help of mathematical expressions and physical interpretations. Various tunable parameters present in this hybrid device widen its applicability in digital and memory applications.

In this article, we have explored effect of scaling length on passive voltage amplification in hetero structure. We have studied effect of scaling on ferroelectric capacitor, reducing the length of capacitor leads to reduction in span of negative capacitance region, which can be authenticated by charge, voltage and energy landscape curves. Also, reducing the length of heterostructure leads to decr...

Improved recycling folded cascode(RFC) operational transconductance amplifier(OTA) is presented in this brief. Performance of the proposed OTA is significantly enhanced in comparison to conventional folded cascode(FC) and recycling cascode(RFC) OTA by employing a dynamic current boosted adaptive bias circuit and positive feedback with an improved current mirror. The proposed design is simulated in a cadence virtuoso analog design environment with SCL $0.18\ \mu m$ standard CMOS technology. Simulation results indicate that the proposed OTA achieves a slew rate (SR), gain bandwidth (GBW), and settling time of $110 V/\mu s$, 224MHz and 14ns respectively at $400\ \mu A$ biasing current that is better than some state-of-the-art recently published designs.

In this paper, we have discussed threshold voltage and drain induced barrier lowering in NCFET. Threshold voltage in NCFET is lower as compared to MOSFET which is mainly because of negative equivalent oxide capacitance in NCFET. Further, we have discussed drain induced barrier lowering in NCFET and MOSFET. An increase in drain bias in MOSFET leads to decrease in threshold voltage and an increase in leakage current whereas in NCFET increase in drain bias leads to increase in threshold voltage and decrease in leakage current. We have obtained a positive value of DIBL factor for MOSFET and negative value for NCFET.

Phase transition FinFET (PT-FinFET) is an emerging steep slope device that utilizes phase transition material (PTM) at the source of the host FinFET to achieve steep switching and boost ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio compared to conventional transistors. Due to nonzero $\rho _{\text {MET}}$ of the assisting PTM, PT-FinFET suffers from low ${I}_{ \mathrm{\scriptscriptstyle ON}}$ as compared to baseline FinFET. To address this issue, we propose, analyze, and mathematically justify a device design exhibiting enhanced subthreshold swing (SS), ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ by exploiting a negative capacitance material at the gate of the PT-FinFET. In the proposed model, critical thickness ( ${t}_{\textit {fe}}$ ) of 3 nm for negative capacitance material was achieved. In comparison with the baseline FinFET and negative capacitance PT-FinFET, the proposed device (NC-PT-FinFET) is able to improve ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio by 3.02 and 2.94 decades, respectively. Furthermore, SS of nearly 10 mV/decade is achieved over 4 decades of drain current with minimum value of 6.8 mV/decade for ${t}_{\textit {fe}}\,\,= {3}$ nm.

Modern wearable devices demand low power high performance medical signal monitoring to achieve efficient and reliable health-care services. The electrocardiogram (ECG) signal which is used to diagnose heart diseases requires 24 hour monitoring. Efficient VLSI implementation of lossless ECG encoder is the critical requirement in wireless health care services. This paper presents an area efficient and high performance lossless ECG encoder that utilizes a single stage Huffman table to provide compressed ECG data. In the proposed ECG encoder architecture, low range of ECG data is encoded via small Huffman table whereas out of range data is segmented into upper and lower parts. These upper and lower parts are encoded by the same Huffman table in the two consecutive clock cycles. This architecture is implemented in MATLAB and simulated with MIT-BIH Arrhythmia database. The simulation results of the proposed ECG encoder show 72.87% more compression over the existing ECG encoder. To evaluate the hardware efficiency, the encoder is implemented in Verilog and synthesized with Synopsys Design Compiler using 90nm PDK. The results show that proposed encoder requires 12.11% less area and provides 2.1X improved performance over the existing encoder.

School of Physics and Materials Science, Thapar Institute of Engineering and Technology, patiala.