Dielectric confinement (DC) effect is a phenomenon in which as the diameter of the silicon nanowire (SNW) decreases, the efficiency of dopant activation in silicon is reduced due to the dielectric surrounding the SNW. Inevitably, saddle-fin cell transistor for high density DRAM has silicon pillars like SNWs which are connected to storage capacitance and bit-line through polysilicon or silicon. In this paper, we implemented a dielectric confinement model in TCAD and fabricated saddle-fin cell arrays and specific test element groups for extracting resistance components using 20 nm technology node. It is found that the DC effect does not significantly affect the resistance values of storage node contact (SNC) and bit-line node contact (BLC) up to 20nm node, but becomes significant beyond sub 20nm node. The DC effect increases the variance of external resistance as well as the resistance value. This result indicates that it is necessary to find a proper solution to mitigate the DC effect, especially when using low-k materials to reduce the parasitic capacitance for sensing margin beyond sub 20nm technology node.

The novel select gate lateral coupling (SGLC) cell has a single poly structure and operates using a lateral coupling between the floating gate (FG) and the select gate (SG) without additional processes on a base platform. In this paper, we have fabricated a pure logic CMOS processed SGLC cell for the first time and compared it with an HVCMOS processed SGLC cell. Because of the thinner gate oxide, the pure logic process fabricated SGLC cell has a lower coupling value than that of the HVCMOS process fabricated cell. However, the logic CMOS process fabricated cell shows a higher current performance than the HVCMOS process fabricated cell having a thicker gate oxide. Thanks to the inverse relationship between the coupling ratio and cell current, and the additional back bias effect, the logic CMOS processed cell gives comparable performance in terms of the programming speed, program-erase threshold voltage (VT) window and cell current. Both types of cells show more than 10 years of data retention lifetime at 85°C.

The authors demonstrated and verified the operation of a SGLC eNVM cell using 3D and 2D TCAD simulations. In addition, we have explained the benefits of the SGLC NVM cell as CMOS process design rules shrink. The novel SGLC cell shows a smaller size than 6T SRAM for beyond the 65 nm technology node. The SGLC cell shows ideal characteristics for eNVM, such as a fast program speed, multi-time programmable support, over-erase free features as well as an SRAM comparable cell size without any additional process steps.