High-NA EUV lithography is currently under development to keep up with device node scaling with smaller feature sizes. In this paper, the most recent advances in EUV patterning using metal oxide resists (MOR) and chemically amplified resists (CAR) are discussed. A newly developed resist development method (ESPERT™) was examined on MOR with 24 nm pitch line and space (L/S) patterns and 32 nm pitch pillars for preparation of high-NA EUV patterning. The patterning results showed improved sensitivity and pattern collapse margin. CAR contact hole patterning at 28 nm pitch was also examined by stochastic lithography simulation. The simulation results indicate that resist film thickness needs to be optimized for target pitches.

Extreme ultraviolet lithography (EUVL) has overcome significant challenges to become an essential enabler to the logic and memory scaling roadmap. Despite its significant progress, resist photo speed, and defectivity remains the main concerns for high-volume manufacturing. To overcome these issues, high-performance EUV resist processes are needed. The high-performance resist process must simultaneously meet multiple requirements, such as a high resolution, high sensitivity, low roughness, low defect level, and good global CD uniformity (CDU). One of the high-performance resist candidates for future EUV scaling, and high NA EUV is Metal Oxide Resist (MOR). In our work, we introduce the new coater/developer hardware and new resist development techniques to improve photo speed, defectivity, and CDU without degradation of roughness in MOR. We will show that the new development methods significantly improve EUV dose to size (DtS) and micro-bridge (MB) while maintaining resist roughness performance post litho and post-etch. The new coater/developer hardware and processes are evaluated through a robust characterization methodology that includes an understanding of the defect modes at ADI (after development inspection) and AEI (after etch inspection), as well its ultimate correlation to electrical yield.

One of the key steps in the pattern formation chain of (extreme ultraviolet) EUV lithography is the development process to resolve the resist pattern after EUV exposure. A simple traditional development process might not be sufficient to achieve the requirements of an ultra-high-resolution feature with low defect levels in high numerical aperture (NA) EUV lithography. In our previous literature, a new development method named ESPERTTM (Enhanced Sensitivity develoPER TechnologyTM) has been introduced to improve the performance of metal oxide resists (MOR) for 0.33 NA EUV lithography by breaking the dose-roughness trade-off. In this work, this development technique was optimised for high-NA lithography to not only keep the advantages of previous ESPERTTM version, but also reduce the defect levels at a higher EUV sensitivity. This is made possible thanks to the capability of the new version of ESPERTTM that can easily remove the residue (undeveloped resist) at low exposure dose area to enhance the developing contrast. Using 0.33 NA EUV scanners at imec on 16-nm half-pitch (HP) line/space (L/S) patterns, with the new development method, EUV dose-to-size (DtS) was reduced roughly 16%, and total after-development-inspection (ADI) defects was reduced by a factor of approximately 7, simultaneously. In another condition, DtS was reduced from 44.2 to 28.4 mJ/cm² (an improvement of 36%), while the number of after-etch-inspection (AEI) single-bridge defects was reduced by half, simultaneously. Using the 0.5 NA exposure tool at Lawrence Berkeley National Laboratory with this new development method, the exposure sensitivity and line-width-roughness (LWR) were both improved by 30% and 21%, respectively. An 8-nm-HP L/S pattern was also successfully printed by this high NA tool. Using a 150 kV electron-beam (EB) lithography system, a 12-nm-HP of pillars was successfully printed on a 22-nm-thick MOR resist with ESPERTTM. With all the advantages of having a high exposure sensitivity, a low defectivity, and an ultra-high-resolution capability, this new development method is expected to be a solution for high-NA EUV lithography.

As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. Additionally, it has become clear that new techniques and methods are needed to mitigate pattern defectivity and roughness at lithography and etching and eliminate film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns [1]. This paper reviews the ongoing progress in coater/developer processes to enable EUV patterning with sub-30 nm line and space and sub-40 nm pillars by using metal oxide resist (MOR). We show that combining new material with optimized illumination and processes helped reduce the minimum critical dimension size, defectivity, and roughness.

Resolution, line edge roughness (LER) and sensitivity (RLS) and defectivity are the well-known critical issues of extreme ultraviolet (EUV) lithography. To break the RLS triangle, metal oxide resist (MOR) is a promising candidate. However, further improvement of MOR process is required for high volume manufacturing to maintain low defectivity. In this paper, conventional and new processes for MOR pitch 32 nm line and space (L/S) and 36 nm pillar patterns was investigated. This new process was able to perform good sensitivity without degrading roughness. In addition, further optimization for underlayer and developer process could mitigate pattern collapses. MOR treatment was evaluated as another technique for roughness improvement. At last, bottom scum defect would be reduced by new process.

Extreme ultraviolet (EUV) lithography has already utilized for high volume manufacturing, and miniaturization by numerical aperture (NA) 0.33 is approaching to the limit. Pitch 24 nm line and space (L/S) resist patterns can be resolved with single exposure at even NA 0.33. However, etch transfer performance to underlayer materials is one of the issues. Especially, in narrow pitch case, it is very difficult to etch due to the lack of resist mask resistance. Therefore, resist pattern thickening process with optimized development process and underlayer state was studied and verified the pattern height impact at our past paper. As a result, it found that combination of the underlayer (UL) kinds and their status was one of the key points to lead high-quality patterns. In this paper, optimized stack structure narrow pitch pattern and lithography performance. As a result, in experiments toward High NA EUV, 24 nm pitch L/S pattern could be patterned (near smallest size by NA 0.33) by selecting the optimal ML/UL combination, and some defect free process windows were kept between defect cliffs.

To mitigate pattern defectivity and roughness at lithography and etch process and eliminate film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns. The ESPERT (Enhanced Sensitivity develoPER Technology) technique has been developed and optimized to fulfil this novel development need. The ESPERT has demonstrated a capability that can enhance the developing contrast between the EUV exposed and unexposed areas. This paper reviews 23 nm pitch line and space and sub-40 nm pitch pillars and hole patterns were realized by optimized illuminators with 0.33 NA single exposure, and we will show the ESPERT helped reduce the minimum critical dimension size, defectivity and roughness at the finer patterns.

Extreme ultraviolet (EUV) lithography has already introduced in high volume manufacturing and continuous improvements has allowed to resolve pitch 24 nm line and space (L/S), pitch 32 nm contact hole and pillar pattern with single exposure at even numerical aperture (NA) 0.33. However, pattern roughness, local critical dimension uniformity (LCDU) and process related defects are still major challenges with decreasing critical dimensions (CD). Pitch downscaling also require the use of thinner photoresist mask to prevent pattern collapse from high aspect ratios. Thinner photoresist mask is challenging for pattern transfer because the resist “etch budget” is becoming too small to prevent pattern break during plasma etch transfer. It is required to investigate a co-optimization of lithography processes, underlayers and etch processes to further EUV patterning extension. In this paper our latest developed technology and process solutions to extend the limits of EUV patterning will be report.

In this talk we present core technology solutions for EUV Patterning and co-optimization between EUV resist and underlayer coating, development and plasma etch transfer to achieve best in class patterning performance. We will introduce new hardware and process innovations to address EUV stochastic issues, and present strategies that can extend into High NA EUV patterning. A strong focus will be placed on dose reduction opportunities, thin resist enablement and resist pattern collapse mitigation technologies. CAR and MOR performance for leading edge design rules will be showcased. As the first High NA EUV scanner is scheduled to be operational in 2023 in the joint high NA lab in Veldhoven, Tokyo Electron will collaborate closely with imec, ASML and our materials partners to accelerate High NA learning and support EUV roadmap extension.

As the semiconductor industry continues to push the limits of integrated circuit fabrication, reliance on extreme ultraviolet lithography (EUVL) has increased. New techniques and methods are needed to mitigate pattern defectivity and roughness using both lithography and etch processes to eliminate film-related defects. These approaches require further improvements to the process chemicals and the lithography process equipment to achieve finer patterns. Additionally, underlayers and resist optimization play a significant role in resist pattern fidelity. This paper reviews the ongoing progress in coater/developer processes that are required to enable EUV patterning by using chemically amplified and metal oxide resists. We will discuss several new techniques for pattern defectivity, roughness, and EUV dose- to- size reduction using coater/developer processes. In addition, we will review our study with various underlayers to enable smaller minimum critical dimension size.