Hole spins in Ge/SiGe heterostructures have emerged as an interesting qubit platform with favourable properties such as fast electrical control and noise-resilient operation at sweet spots. However, commonly observed gate-induced electrostatic disorder, drifts, and hysteresis hinder reproducible tune-up of SiGe-based quantum dot arrays. Here, we study Hall bar and quantum dot devices fabricated on Ge/SiGe heterostructures and present a consistent model for the origin of gate hysteresis and its impact on transport metrics and charge noise. As we push the accumulation voltages more negative, we observe non-monotonous changes in the low-density transport metrics, attributed to the induced gradual filling of a spatially varying density of charge traps at the SiGe-oxide interface. With each gate voltage push, we find local activation of a transient low-frequency charge noise component that completely vanishes again after 30 hours. Our results highlight the resilience of the SiGe material platform to interface-trap-induced disorder and noise and pave the way for reproducible tuning of larger multi-dot systems.

We demonstrate fully crystalline, single-mode ultrahigh quality factor integrated microresonators comprising epitaxially grown Si_0.86Ge_0.14 waveguide cores with silicon claddings. These waveguides support resonances with internal Q >10^8 for both polarization modes, a nearly order-of-magnitude improvement over that seen in prior integrated Si photonics platforms. The maximum Q is 1.71±0.06 × 10^8 for the transverse magnetic (TM) polarization mode, corresponding to a loss of 0.39±0.02 dB/m. Together with silicon's strong Kerr nonlinearity and low losses in the optical, microwave and acoustic regimes, our results could lead to the Si_1-xGe_x/Si architecture unlocking important new avenues for Kerr frequency combs, optomechanics, and quantum transduction.

The extremely high hole mobilities attainable in strained germanium quantum wells (QW) provide a unique pathway to develop novel devices in the emerging field of quantum electronics. A major challenge associated with the growth of Ge QW structures using the industrial standard reduced-pressure chemical vapor deposition (RP-CVD) technique is the incorporation of unintentional impurities in the growing film. We will show that a compromise exists between the growth conditions that minimize the various impurities (mainly O and Si) and the abruptness of the QW. The purity of the incoming gas plays a central role in this compromise and will be discussed.

This paper discusses some design and implementation issues related to GaN micro-LED (μLED) incorporated into the heterogeneous packaging of IBM’s smart and secure sensor platform. For cost effective μLEDs, the sapphire substrate needs to be singulated reliably and with minimum kerf perimeter, be ultra-clean and smooth to allow back side emission without scattering, and high yielding front side flip chip bonding with 20μm C4s on 40μm pitch. The GaN μLEDs are design for low voltage/low power operation with an emission area of 20μm × 20μm with critical current density of ~10nA/μm2. Power and downlink data is delivered to the system via optical energy harvesting by on-silicon carrier photovoltaics and communication photodiode, respectively. Optical amplitude modulated uplink communication by heterogeneous packaging of the GaN μLED with a 14nm CMOS smart chip will be detailed and demonstrated in presentation.

Advancement in microelectronics technology enables autonomous edge computing platforms the size of a dust mote. In article number 2004573, Ning Li and co-workers show that dust-sized photovoltaic cells on a Si substrate can be integrated using a wafer-level-packaging process with other chiplets to achieve high efficiency and high power density. This advancement unlocks the potential of large-scale manufacturing of these compact integrated systems with high performance and low cost.

Nanostructured porous silicon materials have recently advanced as hosts for Li-metal plating. However, limitations involve detrimental silicon self-pulverization, Li-dendrites, and the ability to achieve wafer-level integration of non-composite, pure silicon anodes. compo. Herein, full cells featuring low-resistance, wafer-scale porous crystalline silicon (PCS) anodes are embedded with a nanoporous Li-plating and diffusion-regulating surface layer upon combined wafer surface cleaning (SC) and anodization. LL Lithiophilic surface formation is illustrated via correlation of surface groups and X-ray structure. Low-cost SC-PCS anodes require no composite formulation, and pre-lithiation enables sustainable Li-metal plating/stripping on the lithiophilic surface and in SC-PCS bulk nanostructure. Anodization time and C-rate determined competitive full cell performance: NMC811 | 4800 s SC-PCS: 195 mAh/g (99.9% coulombic efficiency [C.E.], C/3, 50 cycles), 165 mAh/g, 587 Wh/kg (97.1% C.E., C/3 and C/2 rate, 350 cycles), 24 Ω∗cm2 SC-PCS-resistivity (900 cycles); 160 μm LCO | 500 s SC-PCS: 102 mAh/g (94.1% C.E., 1C, 350 cycles).

Conventional light-emitting diodes (LEDs) face an efficiency droop at low current due to non-radiative recombination overtaking radiative recombination at low carrier density. To overcome this universal problem, we develop LEDs with high efficiency at ultralow current and voltage, using a novel quantum well design and high-quality interfaces to suppress non-radiative recombination and enhance radiative recombination. The device exhibits close to unity internal quantum efficiency at a low current density of <1 × 10 −4 A cm −2 , more than three orders of magnitude lower than conventional LEDs. The LED bias voltage is reduced to ~30% below the photon voltage ( hν / q ). Wireless communication is demonstrated at these low-power conditions, which enables new applications in smart dust and sensor networks 1 – 6 , low-cost block chain and authentication 7 – 9 , medical applications 10 , 11 and wherever high efficiency at low power is needed. New phenomena such as high-efficiency electroluminescent cooling becomes possible as the LED unity internal quantum efficiency extends to smaller voltage and current.

Silicon based complementary metal-oxide-semiconductor field-effect-transistor (CMOSFET) technology has continued to progress unabated for last five decades despite various challenges arising due to extreme scaling. Pervasive use of Si technology is evident in a large spectrum of products ranging from high end mainframe and server computers for businesses to laptops, smartphones, and internet of things (IoT) for consumer-oriented products. There is an ever-increasing demand to improve Si device performance for the above described and future products. Strain engineering is one of the key aspects to improve transistor performance. In this review, we describe strain engineering in silicon based advanced CMOS technology, which has evolved from conventional two-dimensional (2D) MOSFET structure to 3D FinFET structure. The impact of shrinking dimensions of scaled FinFETs on channel strain engineering as well as options for strain engineering in future CMOS architecture are described. Finally, strain engineering in non-silicon based functional materials such as gallium nitride (GaN) and 2D materials will be briefly discussed.

Historically, haze metrology on KLA-Tencor Surfscan® unpatterned wafer inspection systems is the preferred inline non-destructive method for ascertaining crystal quality of epitaxial deposited films. However, this metrology is limited to unpatterned blanket wafers. This paper describes a non- destructive inline optical methodology for measuring epitaxial quality of both blanket and patterned wafers using a novel fast turnaround machine learning method that can be applied to patterned and unpatterned substrates by utilizing the background noise obtained during broadband plasma optical defect inspection. This machine learning method is an innovative nuisance filtering algorithm used in inline defect inspection tools, named iDO™ 2.0 (inLine Defect Organizer™). The study showed a promising machine learning approach that repeatably measures low and high defect densities which are consistent with Secco etch data.

Wearable sensors can provide important human physiology and activity data and therefore have promising applications in healthcare, entertainment, and security. Here, we report the design, fabrication, and characterizations of a thin silicon film sensor for wearable sensor applications. Temperature, light, and strain sensing capabilities of the thin film of doped silicon, fabricated using a controlled spalling process, were fully characterized. An n-doped silicon thin-film sensor prepared with the spalling technology exhibited a temperature coefficient of -0.44%/degrees C. The sensor also showed excellent light sensin response in an illumination range from 110 to 1710 cd/mm(2). The ratio of the electrical resistance changes over the applied forces was measured to be around 0.6%/N.

Leakage in Si/SiGe CMOS FinFET is examined. Si cap passivation effectively improves SiGe pFET Dit, subthreshold slope, and mobility, which improves pFET DC performance by 20%. SiGe GIDL is higher than Si by a factor of 9, though GIDL is limited to 50pA/um. SiGe GIDL reduction knobs to meet Si counterpart are demonstrated. The results open the door to the next stage of Si/SiGe CMOS FinFET such as low power and low leakage applications.

In this research study, we present comprehensive characterizations of flexible silicon sensors fabricated using controlled spalling which uses fracture to produce thin films of single-crystal silicon directly from a bulk substrate. We characterized the property of the thin silicon film for sensing strain and temperature. The flexible sensor exhibits high sensitivity with a temperature coefficient of resistance of -0.16/°C, which is desirable for targeted health monitoring applications.

Successful wafer-scale layer transfer from high-quality 2-in. diameter bulk gallium nitride substrates was demonstrated using the Controlled Spalling technique. The crystal quality of both the as-fractured bulk substrate and the spalled GaN film was assessed using transmission electron microscopy analysis, and the defect density was below the detection limit (mid 107 cm−2) for both samples. By using the experimentally determined critical conditions for tensile stress and thickness of the Ni stressor layer, an effective fracture toughness KIC of 1.7 MPa m could be calculated for [0001] fracture using the Suo and Hutchinson mechanical model. The resulting in-plane contraction of the GaN film after spalling permitted a novel method for measuring film strain without knowledge of the elastic properties of the material. This was used to measure the Raman E2(high) peak shift coefficient of Δω(cm−1) = 1411ε which, when converted to a stress coefficient (2.95 cm−1/GPa), was in agreement with only one other literature value.

Copyright: © 2017 Sadana DK, et al. This is an open-access article distributed under the terms of the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are credited. The breath taking progress in CMOS scaling over last five decades has made it possible to shrink complex digital integrated circuits (ICs), such as a microprocessor into dimensions that are approaching a dust particle (<1 mm). For example, the latest 10 nm CMOS product is expected to have ~ 100 million transistors/mm2 (1). This makes fabrication of highly advanced smart dust equipped with a low-power (μW) micro-processor a reality and at a cost of less than a dime! Such unimaginable cost reduction is achievable because a 300 mm Si wafer can easily accommodate over 100,000 advanced ICs on a foot print of <0.8 mm × 0. 8 mm. This allows the recent emergence of Internet of Things (IoT) to be expanded using the “smart dust”. Continued proliferation of IoT is expected to exploit advances in smart dust and low-power wireless communication technologies in conjunction with progress in data security. The impact of IoT in monitoring and controlling various environments, such as agricultural fields, medical, healthcare, manufacturing plants, transportation systems and sending continuous streams of accurate and real-time data can be truly transformational (Figures 1 and 2).

Flexible and stretchable electronics are becoming increasingly important in many emerging applications. Due to the outstanding electrical properties of single crystal semiconductors, there is great interest in releasing single crystal thin films and fabricating flexible electronics with these conventionally rigid materials. In this study the authors report a universal single crystal layer release process, called “3D spalling,” extending beyond prior art. In contrast to the conventional way of removing blanket layers from their substrates, the new process reported here enables 3D control over the shape and thickness of the removed regions, allowing direct formation of arbitrarily shaped structures of released film and locally specified thickness for each region. As an exemplary demonstration, silicon flexible tactile sensors are fabricated with sensitivities comparable to those of high performance sensors on rigid substrates. Finite element modeling indicates that the size and thickness of the selectively released features can be tuned over a wide range.

Electron channeling contrast imaging (ECCI) is emerging as a technique for rapid and high-resolution characterization of individual crystalline defects in a scanning electron microscope. However, the application of ECCI to semiconductor materials has been limited to bare samples in plan-view geometry. In this paper, two modalities of this technique are demonstrated with relevance to semiconductor manufacturing and failure analysis: (1) The use of ECCI to reveal misfit dislocation defects along a cleaved cross-section of a SiGe compositionally graded buffer grown on Si and (2) plan-view imaging of misfit dislocations in metamorphic SiGe/Si layers covered by amorphous oxide layers, where the partial loss of contrast due to the oxide layers is quantified and the effect of the beam accelerating voltage is studied. These results demonstrate the power of ECCI in inspecting crystallographic defects non-destructively over large areas, which is highly desirable for substrate quality control in manufacturing of products based on crystalline materials.

Fully functional thin-film blue LED was fabricated by novel means of (1) performing epitaxial growth of a single crystalline InGaN/GaN heterostructure on a recycled graphene/SiC substrate (2) followed by release and transfer of the heterostructure.