In this paper, we present the first-ever commercially available embedded Microcontrollers built on 90nm-node with silicon nanocrystal memories that has intrinsic capability of exceeding 500K program/erase cycles. We also show that the cycling performance across temperature (-40C to 125C) is very well behaved even while maintaining high performance that meets or exceeds the requirements of consumer, industrial, and automotive markets. In specific EEPROM implementation, such high endurance is capable of delivering in excess of 200M data updates. In addition, we also demonstrate that the nanocrystal flash memory is highly scalable to the next generation nodes and the scaling can be accomplished without degradation of program/erase speed, endurance and reliability.

This paper reports on recent bitcell optimizations that improve drive current and program performance. The 16 Mb and 32 Mb array results are best to-date for nanocrystal memories and suggest a robust, reliable array operation.

We present a split-gate based NOR flash memory array with silicon nanocrystals as the storage medium. 128 KB memory arrays have been evaluated with this technology and the results presented here show a nanocrystal memory that has been demonstrated to achieve a minimum 1.5 V operating window that is maintained through 10 K program/erase cycles; well controlled array threshold distributions; fast source-side injection programming (10-20 us); fast tunnel erase into the gate; and robust high temperature data retention for both uncycled and cycled arrays. Results presented here with focus on the array operation demonstrate the maturity of this technology for implementation into consumer, industrial, and automotive microcontrollers.

This viewgraph presentation describes radiation tests of nanocrystal (NC) memory for space systems. A nanocrystal test chip was bombarded by heavy ions from a cyclotron.

Advanced nanocrystal nonvolatile memories have been exposed to heavy ion bombardment. They appear to be promising candidates for future spacecraft electronics.

Data Retention continues to be a reliability concern for flash memories, especially given the challenge of characterizing the lifetime for stress induced mechanisms like Low Temperature Data Retention (LTDR) that can not be accelerated using conventional means. There have been numerous reports on this mechanism, which have for the most part attributed the leakage to the stress from Fowler Nordheim Tunneling (FNT). In this report we apply E-field acceleration methods to large memory arrays to compare the anomalous leakage rate following FNT to that produced by Channel Hot Electron (CHE) stress. We show that the oxide leakage following CHE stress exhibits characteristics similar to that from FNT stress although at a reduced rate. The leakage from CHE stress should be included with other considerations related to LTDR when scaling floating gate NVM technologies.