This paper reports a novel co-design methodology for signal integrity analysis considering thermal effects. Our analysis focuses on practical high-speed interconnect topologies. To ensure reliable and efficient system design, we introduce an efficient electrical-thermal methodology (EEM) for high-speed PCB interconnects. Using our proposed EEM, we perform electrical-thermal co-simulation to ensure efficient design and performance.

In this paper, an accurate modeling of on-chip copper interconnects with surface roughness is performed considering the parametric variability. This modeling is highly accurate as per-unit-length parameters of the on-chip rough copper interconnects are extracted via full wave EM solver. Further, a space-mapped artificial neural network (ANN) is developed for accurate prediction of eye height and eye width from the geometrical and material parameters of the rough copper interconnects. The novel space-mapping ANN developed in this work is more efficient in terms of accuracy and requires fewer training samples when compared to conventional ANNs.

In this paper, an artificial neural network model is developed to predict the statistics of the optimal number and size of repeaters required to minimize the power delay product (PDP) of on-chip hybrid copper-graphene interconnect networks when subject to parametric uncertainty. The proposed ANN model is a composite of two smaller ANN models. One ANN model is used to emulate the per-unit-length parameters of the interconnects as functions of the geometrical, physical, and material parameters of the network. A second ANN model takes as inputs the outputs of the first ANN model and predicts the corresponding optimal number and size of the repeaters required in the network. Overall, the composite ANN model enables the use of analytic expressions instead of expensive and repeated full-wave electromagnetic (EM) simulations to solve the repeater optimization problem. This composite ANN model is used in a Monte Carlo framework for efficient statistical analysis.

It has reached a period when the search beyond silicon for utilizing it in a transistor has increased genuine significance. Graphene is described as a crystalline allotrope of carbon with two-dimensional properties arranged in the hexagonal lattice form. It’s one of the uses in designing field-effect transistors (FET) such as graphene field-effect transistors. It is explored for the future of flexible electronics devices applications due to the promising graphene attributes. There is some parameter that decides the performance such as speed, uniformity, and reliability of the GFET. One can use graphene field-effect transistors (GFET) to design analog and digital applications for future technology nodes. In this paper, we present a mathematical model of flexible bilayer dual-gated graphene FETs and implement it in a Verilog–A.

At high-speeds, careful analysis is required at the design stage to ensure robust signal integrity (SI) in high-speed printed circuit boards (PCBs). Signal loss in PCBs is predominantly due to conductor loss, dielectric loss and impedance mismatch. In this paper, thermal impact on loss and impedance is studied. In that, thermal sensitivity for standard loss, mid-loss, low-loss and ultra-low loss dielectric materials is studied. It is observed that ultra-low loss materials are less sensitive as compared to standard loss materials. Also, thermal impact on impedance and loss in transmission lines, vias and SMT pads is analyzed.

At sub-22nm technology nodes, size effects play a prominent role in the performance degradation of Cu interconnects. Several scattering mechanisms contribute to size effects, including surface roughness and grain boundary scattering as grain sizes in Cu decreases with reduced line widths. Due to these scattering phenomena, the resistivity of Cu interconnects increases drastically, which leads to electrical and thermal performance degradation and reliability issues. To address these limitations, researchers have proposed Cu-Graphene hybrid interconnects, where the line resistance due to Cu and Graphene is connected in parallel leading to smaller effective resistances. In this paper, we present analytical models of the reduction in effective resistivity obtained due to enlargement of grain size. The reduction in effective resistivity is due to the hybrid interconnect geometry and grain size enlargement. We present a qualitative analysis for the resistivity, mean free path, delay and energy delay product of the three interconnect technology nodes from 22nm to 7nm Cu widths. Our analysis shows that Cu on-chip interconnects with Graphene as a barrier layers shows 47%, 30% and 19% improvement in resistivity, delay and energy delay product respectively due to grain size enlargement at 13nm technology node.

Historically, signal integrity (SI) modeling and analysis was performed standalone without considering non-electrical aspects of the design. Going forward, this approach may not be viable to model high-speed serial links. Increased demand for higher CPU core count is resulting in higher wattage CPUs. This in-turn is increasing the number of phases of voltage regulator module (VRM) driving higher thermal footprint for the design. Increase in temperature impacts high-speed interconnect performance adversely. Modeling interconnects for worst-case operating temperature can be unrealistic and could lead to over-design of a channel. In this paper, a Multiphysics approach is proposed to model next generation high-speed interconnects. Computational fluid dynamics (CFD) is used to determine the temperature gradient in the channel and thermo-electrical co-analysis is proposed to accurately predict the interconnect signal integrity (SI) characteristics. A realistic test case is used to demonstrate the importance of proposed Multiphysics co-analysis for different data rates.

As signal speeds increase, small imperfections start to dictate the performance of interconnects. Thermal effects are an inseparable aspect of interconnects due to self-heating caused by the flow of current, and due to environmental heating in high speed designs. This paper presents in detail, thermal effects and their impact on insertion loss, crosstalk and phase of high-speed signals. The paper also describes the thermal sensitivity on various aspects of interconnect design such as inter pair spacing, trace height, and dielectric thickness. For our analysis, simulations were performed using field solvers for temperatures ranging from 20°C to 100°C. Finally, results are analyzed with percentage variation in copper loss versus dielectric losses.

Aggressive scaling of on- chip interconnects results in significantly higher coupling capacitance, which results in crosstalk effects as we enter the end-of-the-roadmap era. Moreover, surface roughness is seen as a major contributor to conductor losses that further exacerbates these crosstalk-induced effects. This article reports an exhaustive analysis of crosstalk-induced effects, considering interconnect surface roughness at current and future technology nodes (i.e., 13 and 7 nm), for on-chip global copper interconnects. The role of repeater insertion in rough interconnects is also presented in our work. For our analysis, we have used an aggressor-victim-aggressor three-line bus architecture and FINFET-based driver circuits with binary input logic. Our results show that surface roughness degrades typical interconnect performance metrics i.e., worst case delay, bandwidth density (BWD), power consumption, and power-delay product. At a 7-nm technology node, average worst case crosstalk delay and power consumption increase by 17x and 9x, respectively, when compared to smooth interconnects. Similarly, due to surface roughness, BWD reduces by nearly 17x for 7-nm global interconnects. For data rates of 0.2 Mb/s, eye height and eye width are reduced by 73% and 54%, respectively, in the worst case scenario for 7-nm global lines. Finally, we showcase the role of repeater insertion in enhancing performance metrics, in which crosstalk delay and power delay products are significantly improved (by 85% and 99%, respectively) at a 7-nm technology node.

In this paper, crosstalk induced effects in a 3-line bus architecture for global interconnects has been investigated. The dimensions of global level Copper (Cu) interconnects at 22nm technology node are taken as per ITRS. Crosstalk effects have been analyzed for both repeated and unrepeated lines in ternary logic. We have compared crosstalk performance and signal integrity metrics for Cu interconnects with rough as well as smooth surfaces considering Carbon Nanotube FET-based drivers and receivers at 22nm node in ternary logic. Our simulation results show that worst case crosstalk delay, power delay product and number of repeaters used in Cu interconnects with rough surfaces are significantly higher than smooth interconnects. Also, bandwidth density, eye height and width are considerably degraded due to roughness.

In this paper, we present the effect of sidewall roughness, formed by Bosch etching, on the performance of TSVs for frequencies up to 100GHz. Industry standard EM solvers, Ansys HFSS and Q3D extractor are used for our analysis. We present the effect of sidewall roughness on the RLC parasitics, delay, energy-delay product (EDP), insertion loss (S-21) and return loss (S-11) for broadband frequencies up to 100 GHz. Our results show that for chip level TSVs at 100 GHz and 72nm sidewall roughness, insertion loss increase by 7% and return loss decreases by 13% when compared to that of smooth TSVs. Similarly, for wafer level TSVs, insertion loss increases due to roughness. Resistance increases by 1.3X and 1.5X at 100 GHz for wafer level and chip level TSVs, respectively. Energy delay product (EDP) also increases by 1.3X and 1.56X at 100 GHz for wafer level and chip level TSVs, respectively, due to increase in resistive loss. Finally, we present the computational overhead occurred in EM simulations of TSVs with sidewall roughness.

Human recognition through iris has gained allot of attention. This paper presents an efficient approach for recognition which includes segmentation, enhancement, feature extraction and recognition. Before feature extraction the image is enhanced using Contrast Limited Adaptive Histogram Equalization (CLAHE). Iris features are extracted using Scale Invariant Feature Transform (SIFT) which is invariant to scale and somewhat invariant to rotation and shown robustness to affine distortion .The advantage of proposed method is accuracy and simplicity. The system is tested using CASIA database version-4 for experimental results.

Traffic Jam is a crucial problem which is arising day by day in the whole world to overcome this problem many sensors or many algorithms have been developed for the detection of traffic jam. These sensors and algorithm played an important role in Traffic Jam Detection in every region in terms of accuracy, time of detection, signal management. This paper presents a review to the various algorithms proposed in the past.

As in today’s life security is main concern. So, a lot of researches are going in the field of security like password, security question, pattern matching and a very important approach is biometric security. So my work is to study about the palm print recognition to identify human. Palm print recognition system has proved its efficiency with many machine learning techniques like LBP, Repeated line tracking, junctions point matching. This paper is a comparison of different techniques. Previous research on palm print shows that palm codes from different palms are similar, with 〖45〗^°streaks.