5G antenna array covered by a novel frequency selective surface(FSS) is proposed in this paper for 5G antenna array applications. Proposed FSS has a pass-band between 3.3GHz to 3.8GHz with the transmission coefficient greater than −0.5dB, which has negligible impact on the antenna pattern, and the reflection coefficient of the FSS is greater than −1dB between 0.5GHz to 2.2GHz, which serves as a reflector for other band antennas. The antenna array below FSS consists of four elements operated in band of 3.3–3.6 GHz, and gains above 10dB are achieved with no pattern distortion.
The performance of the chirp stepped signal (CSS) is investigated in this paper. Based on the ambiguity function theory, a 60GHz radar system performance with CSS, such as, distance, speed and angle detection are firstly analyzed and then simulated and experimental verified. Finally, using our designed CSS, a higher signal-to-noise ratio (SNR) and improved range detection capability are obtained under the condition of low instantaneous bandwidth when compared with the FMCW signal. Our results show that the CSS has a good potential for 60GHz millimeter radar applications.
In Co-Packaged Optics (CPO) where optical devices and ICs are attached to a common base substrate, there are requirements to keep the temperature of high-heat-dissipating ICs as low as possible and also to keep the temperature of optical devices constant. We propose two solutions to meet these two requirements and show the effect of two solutions by simulation.
With the ever-increasing data rates, interconnect performance predictability becomes more and more challenging. Therefore, along with an accurate methodology, the quantification of measurement reproducibility and its impacts are essential in almost all aspects of high-speed interconnect validation. This paper investigates the reproducibility of S-parameter measurements before and after 2x-Thru de-embedding, and illustrates a multimetric correlation with uncertainty analysis.
SoC design, validation, and manufacturing teams all need to work in tandem to ensure a successful product is released to the market. Pre-silicon and post-silicon validation is critical and is performed to ensure minimal Si re-spins at the fabrication and avoid any design bugs reaching the end customer. The post-silicon debug of various power failures issues related to analog supply exhibiting random signatures induced learnings that can help expedite changes in post-Si validation and high-volume screening, Discussed in detail are the debug efforts to identify one of the many Analog Generation Supply (AGS) noise failure and isolation. The paper elucidates reports of the proposed defects and their various bearings, issue root causes, and issue validation suite formation.
This paper presents a small size cylinder resonant cavity with metal posts embedded for detecting the concentration of aqueous solutions. Compared with a regular cylinder cavity operating in the same mode TM 011 , the electrical field is more focused on near the tube containing materials under test (MUT), hence, the sensitivity of the cavity is enhanced. Three types of solutions are simulated including glucose, NaCl, and ethanol, varying in concentration from 0 to 5%, the results show that sensitivity is generally improved compared to the regular cavity, with glucose/water from 14 MHz/1% to 46.5 MHz/1%, NaCl/water from 36 MHz/1% to 162.5 MHz/1%, and ethanol/water from 20 MHz/1% to 66 MHz/1%.
In this paper, we simulate and demonstrate a patterned graphene resonant subsurface terahertz absorber using the finite element method. By adjustment of the parameters of the geometry of the structure, the absorber’s absorption can be tuned well. The structure’s angle of incidence is also evaluated. The structure can be optimally tuned to achieve over 92% absorption at any frequency point in the 1.40 THz to 3.44 THz frequency band. The structure designed by introducing two-dimensional materials has promising applications in terahertz detection and sensing, and can also be used to make filter components.
Determination of electrical property parameters like permittivity and permeability for penetrable materials is very important in many applications. There are several common techniques such as resonant cavity method, free space method, and waveguide method which can achieve the purpose. Partially filled waveguide method is another one that enjoys the feature of reduced fabrication precision requirement for the dielectric sample under test. In the original paper proposing the partially filled waveguide method, only TM modes are considered. Through mode matching analysis, we will show in this paper that both TM and TE modes shall be included in order to obtain a correct result.
Data rates in high-speed interfaces like upcoming PCIe Gen6, SERDES, Ethernet are continuously increasing, and the design specifications are becoming more stringent to ensure required performance. Any small variation in the specifications will have significant impact on signal integrity and affect the performance. This means that the total insertion loss, ISI, non-ISI jitter in the entire interconnect should be improved.IC package plays a key role in signal integrity of the high-speed signal and there is a need to have low loss channel. Standards like PCIe have a loss requirement of 4 dB combining silicon and package, in case of non-root complex. Recent developments suggest new design trends for multi-chiplets in a single package with increasing package sizes, which can make it extremely difficult to predict insertion loss specifications. Conductivity, dielectric properties, and loss tangent drives the overall loss per unit length and the current low-loss materials have insertion loss of around 1 dB per 10 mm. While many advances have been reported in the literature, scope for improvement exists and conventional approaches of lowering DF of dielectric material or reducing the surface roughness of Copper have helped but are not adequate for the demands of high-speed interconnects. This paper proposes a novel approach by using hybrid Copper-Graphene package interconnects, which helps in reducing signal losses and improves the overall performance of the system.
A dual mode digital power gate (PG) and linear low drop-out regulator (LDO) is implemented on Intel ® next generation™ microprocessor to enable different IPs on the SoC to operate at their minimal voltage levels. This paper discusses post silicon debug and validation techniques to characterize an integrated dual-mode voltage regulator. Performance metrics such as mode transition, power saving, circuit stability and voltage droop are measured and established in this work. These techniques in general can be applied to an integrated linear voltage regulator. The regulated modes are used when load current or ∂i/∂t is low thus allowing better power management in deeper package core states. Measurement shows 11% power saving in the allocated power budget in PKGC10 when voltage regulator is enabled to regulate at 0.7volt output.
As the signaling speeds continue to increase, maintaining Signal Integrity (SI) for the complete customer design space is a huge challenge. These constraints, along with the limitations of traditional methods of design space inclusion and channel behavior prediction pose significant risk to system design. Specific focus is needed on design space utilization techniques used for factoring in platform variability. Interfaces like PCIe Gen5/Gen6/Gen4 etc. exhibit higher order behaviors that can’t be modelled by current prediction algorithm like Response Surface Method (RSM). This leads to inaccurate system behavior understanding and results in unreliable platform design recommendations. To minimize design risk and achieve highly reliable scaling of Platform Design Guide (PDG) solution, this paper discusses the implementation of an Artificial Intelligence (AI) based methodology to cover complete design space and predict higher order system behaviors with high accuracy. Current SI method involves RSM type Design of Experiments (DOE) creation and results prediction using second order RSM as shown in Fig. 2(a). It has limitations since RSM uses only three variable levels therefore doesn’t cover the entire design space. It can only model up to second order system behavior. These issues can be addressed using proposed AI based methodology shown in Fig. 2(b). These AI techniques have been encapsulated into an AI based tool called Fitpro which fully automates space filled DOE creation and SI results prediction. Fitpro significantly reduces manual interventions and positively impacts efficiency.
In order to simulate the influence of the thermal effects of a patch antenna on its electromagnetic radiation performance, the discontinuous Galerkin time domain (DGTD) method and finite element time domain (FETD) method are employed to implement electromagnetic-thermal co-simulation. The Maxwell equation is solved by DGTD method, while the heat conduction equation is solved by FETD method. The electromagnetic and thermal simulation are linked by loss power of material and temperature dependent conductivity. Numerical results show that the radiation pattern will change if we consider the thermal effects of the patch antenna.
In this paper, we propose a low-profile planar dual band WLAN antenna application on wireless audio. In order to offset with the frequency-shift effect caused by plastic material, the frequency was designed higher than the default application frequency to facilitate/enable the application with added plastic material. The Default application frequency 2.4 GHz & 5 GHz for BT and WIFI, adjust the impedance matching by adjusting the coupling using slot of the two structures on the dipole antenna, so that the energy can be transmitted most effectively.
It is increasingly challenging to satisfy the requirements placed on the power delivery network for a multilevel hierarchical system, due to aggressive voltage scaling and stringent limits on the chip-level voltage droop. This paper presents a methodology to obtain the minimal number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupling capacitors to meet a user-specified target impedance. The number and location optimizations are performed using nature-based and Bayesian optimization algorithms along with the quantitative comparison of results.
This paper presents a novel three-dimensional frequency selective surface (3-D FSS) dedicated to highly integrated package in Sub-6G communication applications. The structure operates between 3.3 GHz and 3.8 GHz with two stopbands on each side. A stable response under the incident angles up to 50° is shown through an electromagnetic simulator analysis. The in-band insertion loss is less than 0.65 dB and the out-of-band insertion loss is more than 10 dB for both TE and TM polarizations under the incident angle up to 50°. Moreover, this novel structure is insensitive to all polarization and has a unit cell size of 0.07λ. All these results indicate that the proposed FSS is a good candidate for radiation leakage suppression in Sub-6G highly integrated package.
As we move into the complex design of high-speed IOs working at increased datarates of more than 100G, power delivery network (PDN) optimization becomes more challenging. To meet the stringent Power Delivery Network noise specifications, we make sure that the impedance seen by the device meets the target impedance, by optimizing the decap (decoupling capacitor) requirements at PCB, package, and die. Package level decap optimization is one of the major challenges to be addressed to meet the voltage ripple requirements with minimal BOM(Bill of Materials) cost. Here we propose a method to perform the decap optimization of the Serdes with a shared power delivery network, considering the impact of power supply noise coupling in multi-lane shared SerDes. This paper analyses the impact on ripple voltage from different voltage noise sources and explains how the PDN design accuracy can be improved in the frequency domain without having to run the transient simulation every time, which is a time-consuming process and poses challenges to Time-to-Market (TTM) concerns.
In this paper, we propose a deep reinforcement learning (DRL)-based multi-power distribution network (PDN) decoupling capacitor design optimization method considering transfer noise in 3D-ICs. The transfer noise from multi-PDN with vertical structures could cause system failure, the entire simultaneous switching noise (SSN) with the combined transfer noise should be considered. To address the multi-PDN problem, we use reinforcement learning suitable for solving complex optimization problems. The input dataset and Markov decision process (MDP) were designed to optimize various multi-PDN cases. The 5x4 size of two PDNs with a vertically stacked structure was used for verification. The proposed method successfully optimizes the decoupling capacitors of multi-PDN. In addition, the proposed method was compared to genetic algorithm (GA), the proposed method perfomed better optimization and reduced the time by about 99% compared to GA to 0.08 seconds.
We present an electrical model of tapered differential-multibit through glass vias (DM-TGVs) for high density three-dimensional (3-D) integration. Analytical equations are developed to compute the impedance parasitics of tapered DM-TGVs. Simulations using the 3-D field solver with parameter modifications, such as slope angle of the TGV, type of filler material are used to confirm the scalability of the proposed model. We examine the electrical behavior of tapered TGVs in the frequency domain using the proposed model. Eye-diagram measurements are also used to verify the frequency dependent loss of capacitive-resistive TGV in the time domain.
(Multi-input Multi-output)MIMO technology employs multiple antennas to send and receive signals. Using the MIMO technology, we obtain more data than that using traditional single antennas. Evaluating performance of dual transmitter, isolation in multiple antennas is an important parameter. The coupling effect in MIMO antennas will not only affect the characteristics of the antenna itself, but also the pattern, which will be compressed. In this paper, the PIFA = 1/4λ wavelength is used and realize the miniaturization of the antenna body and the PIFA architecture is beneficial to current distribution, that direct improve the isolation to − 20dB. In this paper, we propose two wide band and high isolation small PIFAs printed on 5G module to cover the 5 GHz ISM band. The module dimensions is 40 mm × 30 mm, antenna area dimensions is 7 mm × 30 mm and has a 100% available wide bandwidth in the range of 5.5 GHz to 6.5 GHz
The performances of Non-Return-to-Zero (NRZ) and Ensemble Non-Return-to-Zero (ENRZ) at the throughput of 112 Gbps per pair (224 Gbps for an ENRZ channel), with three channels of different levels of losses, are investigated. The Frequency Domain Matrix Multiplication (FDMM) channel simulation method is introduced and applied. The simulation results show that ENRZ has a remarkable advantage in terms of channel loss, which becomes more pronounced as channel loss increases. While it might still be challenging for ENRZ to support a full-length backplane at 224 Gbps per Chord™, its supportable range should be significantly larger than NRZ.
