Electroforming behaviours of Ta2O5 resistance switching memory cell with a diameter of 28 nm and different thickness (0.5–2.0 nm) of Ta2O5 layer have been examined. The devices showed a constant forming electric field of 0.54 V/nm regardless of Ta2O5 thickness. The electroforming with negative bias to top TiN electrode was ascribed to electric field‐ driven migration of oxygen vacancies, originally residing near the bottom interface, toward the top electrode interface and formation of conducting filaments. The estimated electroforming energy (0.094–0.14 eV) was favourably compared with the hopping energy of electrons from the VO site to a nearby Ta site. (© 2015 WILEY‐VCH Verlag GmbH &Co. KGaA, Weinheim)

Resistance switching (RS) devices with ultra-thin Ta 2 O 5 switching layer (0.5–2.0 nm) with a cell diameter of 28 nm were fabricated. The performance of the devices was tested by voltage-driven current—voltage (I-V) sweep and closed-loop pulse switching (CLPS) tests. A Ta layer was placed beneath the Ta 2 O 5 switching layer to act as an oxygen vacancy reservoir. The device with the smallest Ta 2 O 5 thickness (0.5 nm) showed normal switching properties with gradual change in resistance in I-V sweep or CLPS and high reliability. By contrast, other devices with higher Ta 2 O 5 thickness (1.0–2.0 nm) showed abrupt switching with several abnormal behaviours, degraded resistance distribution, especially in high resistance state and much lower reliability performance. A single conical or hour-glass shaped double conical conducting filament shape was conceived to explain these behavioural differences that depended on the Ta 2 O 5 switching layer thickness. Loss of oxygen via lateral diffusion to the encapsulating Si 3 N 4 /SiO 2 layer was suggested as the main degradation mechanism for reliability and a method to improve reliability was also proposed.

In this paper, the authors report that 2x nm cross-point ReRAM with 1S1R structure has been successfully developed. Off-current at 1/2 Vsw of 1S1R is one of key factor for high-density ReRAM. NbO2 was chosen as a selector material and off-current and forming characteristics were improved by using stack engineering of top and bottom barriers as well as spacer materials. Finally array operation was characterized with the integration of selector and resistor materials.

In this paper, 5Xnm cross point cell array for the low power ReRAM operation was developed with 1S1R cell structure. Through the optimization of both TiOx/TaOx based-1R and NbO2 based-1S stacks with TiN based-electrode, the world's first and best bipolar switching characteristics with the lowest operation current (20~50uA) and sneak current (~1uA) level were acquired.

We demonstrate a varistor-type bidirectional switch (VBS) with excellent selection property for future 3D bipolar resistive memory array. A highly non-linear VBS showed superior performances including high current density (>;3×10 7 A/cm 2 ) and high selectivity (~10 4 ). The non-linear I-V characteristics can be explained by varistor-type multi-layer tunnel barriers, which were formed by Ta incorporation into thin TiO 2 . Furthermore, the 1S1R device showed excellent suppression of leakage current (>;10 4 reduction) at 1/2V READ , which is promising for ultra-high density resistive memory applications.

A compact STT(Spin-Transfer Torque)-RAM with a 14F 2 cell was integrated using modified DRAM processes at the 54nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of STT-RAM, we estimate that the unit cell dimension below 30nm can be smaller than 8F 2 .

The operating characteristics and retention times of floating body cells and arrays using Z-RAM (R) technology fabricated on a 50nm DRAM process are presented. For the first time, data retention time longer than 8s at 93 degrees C and 1.6V wide programming window are obtained on floating body cells as small as 54nm x 54nm. These results demonstrate the suitability of floating body memories for DRAM applications. These improvements were obtained through optimization of DRAM technology such as junction engineering, thermal treatments, and improved passivation processes.

We investigated whether the fluorine of the field oxide affected gate oxide reliability and some isolation characteristics of metal–oxide semiconductor (MOS) transistors for high-density dynamic random-access memory (DRAM). Fluorine was incorporated during high density plasma (HDP) chemical vapor deposition (CVD) using NF3 chemistry for better shallow trench isolation (STI) gap-filling ability. Considerable fluorine included in the field oxide during deposition diffused from the field oxide to the silicon surface of a shallow trench during the subsequent thermal processes. This fluorine of the field oxide did not degrade the gate oxide reliability such as SILC and charge-to-breakdown characteristics. Moreover, it could improve various transistor characteristics such as the junction leakage, isolation punch-through current and data retention time of a DRAM device. It was inferred that some improvement of the MOS transistor was obtained by the interaction of Si interface traps near the trench wall with fluorine and the reduction of the density of Si interface traps.

Fatigue characteristics of lead zirconate titanate (PZT) films deposited by electron cyclotron resonance plasma enhanced chemical vapor deposition (ECR-PECVD) were investigated. The fatigue characteristics were investigated with respect to PZT film thickness, domain structure, fatigue pulse height, temperature, electrode materials and electrode configurations. The used top and bottom electrode materials were Pt and Rut(2). In the fatigue characteristics with fatigue pulse height and PZT film thickness, the fatigue rates are independent of the applied fatigue pulse height at the electric field regions to saturate the P-E hysteresis and polarization (P*, P<^>) characteristics. The unipolar and bipolar fatigue characteristics of PZT capacitors with four different electrode configurations (Pt//Pt, Pt//RuO2, RuO2//Pt, and RuO2//RuO2) were also investigated. The polarization-shifts during the unipolar fatigue and the temperature dependence of fatigue rate suggest that the migration of charged defects should not be expected in our CVD-PZT films. It seems that the polarization degradations are attributed to the formation of charged defects only at the Pt/PZT interface during the domain switching. The charged defects pin the domain wall at the vicinity of Pt/PZT interface. When the top and bottom electrode configurations are of asymmetric (Pt//RuO2, RuO2//Pt), the internal fields can be generated by the difference of charged defect densities between top and bottom interfaces.