For reliable operation, individual cells of an STT-MRAM memory array must meet specific requirements on their performance. In this work we review some of these requirements and discuss the fundamental physical principles of STT-MRAM operation, covering the range from device level to chip array performance, and methodology for its development.

We report our progress on material improvement, device design, wafer processing, integration with CMOS, and testing of STT-RAM memory chips at 54 nm node with cell sizes of 14 and 28 F2 (F=54 nm). A dual tunnel barrier MTJ structure was found to have lower and more symmetric median spin transfer torque writing switching currents, and much tighter parallel to antiparallel switching current distribution. In-plane MTJ devices write endurance data, read and write soft error rates data and simulation fits, and solutions to the long write error rate tail at fast write speeds are discussed.

STT-RAM (Spin-Transfer Torque Random Access Memory) is a second-generation magnetic random access memory (MRAM) technology that is fast, non-volatile, durable, and scalable to future technology nodes [1-2]. In this paper, we present the latest advances in in-plane and perpendicular STT-RAM development and outline STT-RAM's future prospects, applications and roadmap.

Spin-transfer torque random access memory (STT-RAM) is a potentially revolutionary universal memory technology that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, the non-volatility of Flash, and essentially unlimited endurance. In order to realize a small cell size, high speed and achieve a fully functional STT-RAM chip, the MgO-barrier magnetic tunnel junctions (MTJ) used as the core storage and readout element must meet a set of performance requirements on switching current density, voltage, magneto-resistance ratio (MR), resistance-area product (RA), thermal stability factor (¿) , switching current distribution, read resistance distribution and reliability. In this paper, we report the progress of our work on device design, material improvement, wafer processing, integration with CMOS, and testing for a demonstration STT-RAM test chip, and projections based on modeling of the future characteristics of STT-RAM.

A compact STT(Spin-Transfer Torque)-RAM with a 14F 2 cell was integrated using modified DRAM processes at the 54nm technology node. The basic switching performance (R-H and R-V) of the MTJs and current drivability of the access transistors were characterized at the single bit cell level. Through the direct access capability and normal chip operation in our STT-RAM test blocks, the switching behavior of bit cell arrays was also analyzed statistically. From this data and from the scaling trend of STT-RAM, we estimate that the unit cell dimension below 30nm can be smaller than 8F 2 .

Non-volatile STT-RAM (spin transfer torque random access memory) is a new memory technology that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM and the non-volatility of Flash with essentially unlimited endurance. It has excellent write selectivity, excellent scalability beyond the 45 nm technology node, low power consumption, and a simpler architecture and manufacturing process than firstgeneration, field-switched MRAM. A magnetic tunnel junction (MTJ) device (Fig. 1) is used as the information storage memory element, and its magneto-resistance is used for information read-out. To make the STT-RAM technology competitive with mainstream semiconductor memories, the writing current has to be reduced so that the MTJ can be switched by a minimum sized CMOS transistor. In this paper, we discuss our approaches and results in writing current reduction; device read and write performances; robustness against read disturb switching and barrier break down; and prospects of scaling to future smaller nodes.

The thermal stability of STT-RAM is measured by multiple techniques and compared with theory. The read disturb rate is found to be determined by the standby thermal stability, but the error rate at target read currents is higher than expected. The implication for the design of 1 Gb STT-RAM is that 10 year room temperature data retention as well as 1000 FIT read disturb error rate requires thermal stability of greather than 75.

We quantitatively determine a perpendicular spin torque in magnetic tunnel junctions by measuring the room-temperature critical switching current at various magnetic fields and current pulse widths. We find that the magnitude of the torque is proportional to the product of the current density and the bias voltage, and the direction of the torque reverses as the polarity of the voltage changes. By taking into account the energy-dependent inelastic scattering of tunnel electrons, we formulate the bias dependence of the perpendicular spin torque which is in qualitative agreement with the experimental results.