A scaleable gate array has been designed in half-micron CMOS for a wide range of high-speed and high-density applications. Transistor size and position within the basecell provide an efficient implementation of flip-flops, combinational gates, and memory. Design benchmarks have demonstrated 2700 gates/mm/sup 2/ routed density in a 0.5 /spl mu/m TLM CMOS gate array. Compared to previous 5 V 0.7 /spl mu/m gate arrays, the new basecell provides improvements of 2.5x in density and 30% in speed, at 70% lower power, NAND-2 delays are 170 ps (FO=2, 3.3 V). Metal-programmable two-port SRAM's feature 3.9 ns typical access times. The new architecture has been implemented in a CMOS gate array family which offers up to 1.15 million available gates and 700 I/O positions.

The authors describe the one-micron CMOS technology for a 256 K SRAM (static random-access memory) on SIMOX (separation by implanted oxygen) which produced fully functional devices in July of 1990. An outline of the process sequence, the characteristics of the world's first 256 K SRAM, and a statistical study of across-the-wafer and wafer-to-wafer parametric parameters taken from test die using this process are presented. The availability of a standardized production process and multiple wafer lots consisting of SIMOX material provides a special tool allowing for statistical observations of device processing and wafer preparation characteristics such as single and multiple wafer implants

Summary form only given. The successful design and fabrication of a 64 K SRAM on SIMOX material is discussed. The advantage of the small junction area resulting from mesa isolation is most evident in the very low standby current. An impressively high yield for first-pass material in a research wafer fabrication area was obtained. Aspects of the design relating to the SOI characteristics are discussed and full characterization results are presented.<>

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n+and p+junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n+and p+junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils2feasible with 1-µm design rules, is also discussed.

This paper presents the first measurements of transient radiation effects on SOI discrete devices and an LSI memory. A commercially processed LSI SOI memory, a 4K × 1 SRAM on SIMOX, was tested for SEU, and transient ionizing radiation effects as a function of bias conditions and dose rate. The SEU error rate was found to be between 1.5 and 2.5 × 10-8 errors/bit-day for the 10% worst-case orbit model. The output voltage logic upset level was greater than 1.6 × 1010 rad(Si)/sec for Vcc supply voltage variations of -10% and +20% with Vsub at -10 V. For the discrete devices and memory, the measured transient photocurrents were larger than the calculated volumetric photocurrent generated in the active device region. This increased transient response is postulated to be due to the gain of the parasitic phototransistor of the dielectrically isolated MOS device.

This paper reports on the fabrication of a SOI-CMOS 4K SRAM using the implanted buried oxide SOI technology with a minimum feature size of 2.5 µm. The 4K×1 CMOS SRAM, using a 6T cell which contained n-channel loads and p-channel driver and pass transistors, exhibited a power dissipation of 85 mW at 5V Vdd and an address access time of 55 ns which agreed with the SPICE simulations. Electrical parameters of the buried oxide SOI devices were compared to those of the bulk CMOS devices. Except for an approximately 10% degradation of the carrier mobility and the "kink" effect due to the floating body node, the buried oxide SOI devices were indistinguishable from the bulk devices. The uniformity of the buried oxide SOI device parameters is emphasized.

Improved formulas are obtained to provide more accurate determination of magnetic bubble material parameters such as material length(l)and saturation magnetization(M_{s})based on the measurements of domain stripe width and bubble collapse field. The improvement takes into consideration the effects of finite uniaxial anisotropy parameter(Q)in the formulas. These improved formulas are based on the n...

A numerical model for the simulation of the dynamics and deformations of thin film magnetic domains in magnetic bubble devices is described. The motions of the domain walls are calculated from the total effective magnetic field acting on them; the total field includes the equivalent field of the wall energy, the demagnetizing fields, the bias field, and the nonuniform fields from conductors or other sources. The numerical scheme of time integration of the wall motion is described; the simulated time step is adaptively optimized in the presence of incipient numerical instabilities, which are monitored by means of Fourier transformations. The model was used to investigate collapse and runout of free bubbles and stripeout and replication of domains under current carrying conductors. The results presented show agreement with experimental data.

The micromagnetic model previously reported has been applied to a selection of materials and to an additional wall type. The stability of unichiral (S=1) walls and walls containing a single horizontal Bloch line pair (HBLP) has been studied numerically for Q in the range 1.4 to 4.6, and for material lengths, normalized to film thickness, between 0.05775 and 0.462. Wall structure, in the form of contour maps and profiles of azimuthal angle, have been obtained for walls without and with a 2π twist (HBLP) centered on the film midplane. The dependence of structural quantities on material parameters is also presented. Bubble mobility dependence on quasi-static wall structure was investigated from the point of view of the gyrovector force density concept. The dependence of the peak magnitude of the gyrovector on material length is discussed, and a relief map of the gyrovector magnitude for a wall containing an HBLP is presented.

The micromagnetic model of Della Torre et al. [7] has been extended to include the analysis of bubble collapse and runout and to reduce computation times by making radius corrections. Results were obtained for a range of bubble aspect ratios and quantities describing wall bulging, flaring, and twisting were computed. Data on material parameter effects is also presented. Magnetization orientation angle contour maps over the r-z plane in the wall region are presented. Wall structure was found to depend strongly on bubble aspect ratio as well as on material parameters. Wall bulging increases with decreasing bubble aspect ratio; at Q=2.3, it is about 5% of the bubble radius near collapse, and 1.5% near runout. The wall thickness at the film center is characteristic of a Bloch wall, but near the surface, azimuthal twisting and wall width flaring increase with bubble aspect ratio. Calculated wall area energy densities are lower than those of corresponding wall structures of variational models. For Q=2.3, it was found that the range of bubble stability is smaller than in previous predictions.