Vertically stacked transistors are being explored as potential options for future technologies beyond GAA Nanosheet technology. In this paper, we report our investigation of challenges and opportunities for vertically stacked transistors, with a focus on block level scaling and device performance consideration. At the standard cell level, our DTCO innovation of splitting the power rails can free up a metal track for signal routing. Implementing two circuit rows for complex cells also increases available tracks. At the block level, we performed the routing study through PnR and overcome the shortage of pin access by DTCO innovations, achieving 0.55x area scaling vs non-stack technology. For device design, choices of device structures and materials for each layer are carefully evaluated. SiGe FinFET(p) on Nanosheet(n) is identified as a strong candidate for vertically stacked device architecture. MOL resistance with one-sided power rail is found to be a bottleneck limiting the device performance. Double-sided power rail (DSPR) is introduced for the first time in this work to effectively address the MOL resistance for stacked transistors.

Application of high-frequency ac stress in the place of conventional dc stress is known to decrease the damage caused by self-heating (SH)-induced hot-carrier injection (HCI) in highly scaled MOSFET devices. However, the effect of hot-carrier degradation on short-channel performance is less explored. In this article, a detailed examination of the drain-induced barrier lowering (DIBL) under hot-carrier stress is presented for 14-nm silicon-on-insulator (SOI) n-channel FinFETs. In particular, the influence of SH-enhanced HCI on DIBL is thoroughly investigated for devices with different geometrical parameters including a number of fins, gate length, and so on at different ac stress frequencies. The change in dominant degrading mechanism from bulk oxide trapping to interface state generation under dc and ac stress is shown to affect DIBL severely. Interestingly, the effect of SH on DIBL is in contrast to that in ON-current degradation. Furthermore, time evolution of DIBL degradation for asynchronous stress waveforms is studied for accurate reliability analysis for short-channel devices.

A comprehensive study on hot-carrier degradation (HCD) mechanisms in 14 nm silicon-on-insulator (SOI) n-channel FinFETs is presented. The impact of high-frequency AC stress bias on self-heating (SH) enhanced hot-carrier injection in oxide bulk traps is investigated and compared with the measurement results using the conventional DC stress bias. The influence of SH on electrical parameter degradation due to hot-carriers is shown as an important metric for accurate device reliability analysis. The relative contribution of bulk and interface traps is determined to identify the dominant mechanism responsible for HCD for different device geometries. The device behavior is thoroughly studied under hot-carrier DC and AC stresses for different device design parameters, such as effective oxide thickness, number of fins, and channel length. Based on measured data, we have proposed an empirical model for reliability degradation, which takes into account some of the key device design parameters and stress bias frequency.

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau-Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies.

In this paper, we propose the extendibility of ultra-thin body and box (UTBB) devices to 7 and 5 nm technology nodes focusing on electrostatics. A difficulty in scaling traditional UTBB is the need for SOI scaling to about one fourth of the gate length. We propose a U-channel fully depleted silicon on insulator architecture that starts off with a thicker SOI (8-11 nm) and has a U-shaped channel enabled by a recessed metal gate. This device improves the electrostatics by increasing the overall gate length at fixed metal gate opening, mitigating drain field coupling to the source due to the recessed metal gate region and having thin SOI below the center of the device (4-5 nm). Modeling shows that good electrostatics can be maintained at small metal gate opening to enable pitch scaling. This device provides lower cost options for mobile and IOT technologies.

Terence Hook has been with IBM since 1980, after receiving his ScB from Brown University. He earned his PhD in Electrical Engineering from Yale University in 1986. While at IBM, he has worked on technology integration and device design for bipolar, BiCMOS, and CMOS technologies from 2 μm to 5 nm and beyond. He has authored dozens of conference and journal papers and holds more than 100 patents. He is currently with IBM Research in Albany, NY.

Nanowire field-effect transistors (NWFETs) have emerged as promising candidates for realization of advanced CMOS technology nodes. Due to small nanowire dimensions, NWFETs are vulnerable to the impact of process-induced random local variations, such as the line edge roughness (LER) and random dopant fluctuation (RDF). NWFETs have three different device modes, namely, the inversion mode (IM), the accumulation mode (AM), and the junctionless (JL) mode. In this paper, a 3-D quasi-atomistic LER model is used for the analysis of LER-induced mismatch in JL, IM, and AM NWFETs. We have also compared the impact of 3-D LER with that of 2-D LER. In addition, another emerging simulation methodology known as statistical impedance field method is utilized to analyze the impact of RDF on the three flavors of NWFETs. We show that JL NWFETs have much higher mismatch due to both LER and RDF than their IM and AM NWFET counterparts with otherwise identical device structure.

The impact of back-end-of-line (BEOL) loading on logic performance at the 7nm, 5nm and 3nm technology nodes is evaluated using a combination of ab initio, finite-element and circuit analysis methods. The effects of processing variations, including line-edge-roughness (LER) and line height variation (LHV) on line resistance and overall frequency performance are quantified at each technology node. We find that barrier material optimization beyond the 5nm node can reduce via resistance by as much as 26%, resulting in a ~2 % performance uplift. Depending on amplitude, the combined effects of LER and LHV can result in a >25% line resistance penalty beyond the 5nm node and a corresponding 8% performance penalty.

Vertically stacked junctionless accumulation mode (JLAM) nanowire field effect transistors (NWFETs) outperform inversion-mode (IM) NWFETs below 10-nm technology nodes, but the vertical stacking of nanowires (NWs) has a constraint of position dependent drain current. This paper encompasses: 1) extensive investigation of the impact of series resistance on IM, JL mode, and JLAM NWFET architectures; 2) a proposed approach to mitigate the series resistance; and 3) linearity assessment of stacked JLAM-NWFET for radio frequency(RF) applications. We have suggested that by decreasing the channel doping in the bottom NW with respect to the top NW in a stack, the current can be significantly improved along with the reduction in series resistance. This improves the overall uniformity of drain current in each NW for stacked JLAM-NWFET. The linearity performance of the device is assessed in terms of following figure of merits (FOMs): IIP3, 1-dB compression point, and higher order derivative of transconductance g(m2) and g(m3). These FOMs are evaluated through numerical simulations using Sentaurus Technology Computer-Aided Design to confirm the robustness of the device against intermodulation distortion making it suitable for low power radio frequency integrated circuit design applications. The proposed solution allows higher drive current, improved linearity, and thus lower distortion in stacked JLAM-NWFET.

Parameter variations in the transistor characteristics with new materials and process steps pose an increasing challenge for CMOS scaling to nanometer feature size. Alternate channel materials such as silicon-germanium (SiGe) for p-type field effect transistor (pFET) at 32 nm and beyond are useful because of higher mobility and lower threshold voltage (V-T) but suffer from higher gate-induced drain leakage (GIDL) and could be a source of additional variability. In this paper, experimental results, a noise-like approach called the statistical impedance field method, and atomistic kinetic Monte Carlo simulations are used to report that the elimination of prehalo Ge preamorphization implant (PAI) from the SiGe pFET process flow reduces GIDL and its variation due to systematic variations in gate length and width but increases the time-zero (static) random GIDL and performance variations. This is primarily due to random dopant position fluctuations in the extension region for off-state leakage (I-OFF) variability and in the halo region at the drain sidewall for V-T variability. However, the increase in random variability without Ge PAI reduces for lower supply voltages and, thus, offers advantages of reduced GIDL with the same electrostatics, lower systematic variations, and similar I-OFF random variability for scaled voltages.

In this letter, we have investigated the RF performance of a negative capacitance FinFET (NC-FinFET) using BSIM-CMG compact model extracted from DC and RF measured data of 10-nm technology node devices. This physics-based RF model is then coupled self-consistently with the Landau-Khalatnikov equation to obtain the RF NC-FinFET model. For the first time, we report, here, the impact of ferroelectric thickness (t fe ) scaling on RF performance of NC-FinFET and find that NC-FinFET's cutoff frequency (f T ) is a function of t fe . We also observe that the self-heating effect in NC-FinFET increases with increase in t fe , mainly due to increase in DC current, which can be easily compensated by decreasing supply voltage. Finally, we show that NC-FinFET can achieve similar analog/RF performance as the base FinFET, even at a reduced V DD .

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts.

We investigate the channel material dependence of wave function deformation scattering (WDS), a phenomenon that occurs when the shape of the carrier wave function is forced to change as the channel is traversed. Line-edge roughness (LER) is one nonideality that can induce WDS in confined device geometries. We perform nonequilibrium Green's function simulations of ensembles of ultrascaled Fin Field Effect Transistors that exhibit correlated LER to determine the resulting on-current distributions. By considering various channel materials, we demonstrate two trends. First, WDS has a greater impact when the transport effective mass of the channel material is low, due to stronger coupling between conducting subbands. Second, WDS has a greater impact when the confinement effective mass of the channel material is high, due to the presence of more conducting subbands, which further enhances coupling.

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Vertically-stacked horizontal gate-all-around (GAA) Nanosheet structures have been recognized as good candidates for beyond the 7nm technology node to achieve improved power-performance and area scaling compared to FinFET technologies. Full realization of device-performance entitlement in high-performance and high-density chip designs is, therefore, of critical importance. In this paper, we present a quantitative performance evaluation of horizontal Nanosheet structures focused on key design styles as well as unique Nanosheet challenges such as gate-resistance. This analysis was performed with a fully developed design kit over a wide range of sub-7nm design, including various cell heights, as well as design features such as M1 power staples and performance-aware designs for smaller track cells.

This paper demonstrates the first reliable and low cost airgap BEOL technology, generated at extremely tight dimensions (48 nm pitch) in Cu/ULK. This provides 20% nested-line capacitance reduction relative to the ungapped Cu/ULK baseline. This result is of critical importance, as it validates that airgaps can be extended down to ultrafine wire levels, such as for the 10 nm technology node. Current technologies implement airgaps only at fat-wire levels; however, a significant enhancement in chip performance can be gained by including airgaps in the finest wiring levels as well. To achieve this, we benefitted from several elements which address various process, integration, and reliability challenges associated with airgap formation at such small dimensions. We present data and explanations of these solutions, and their impacts on yield, performance, defectivity and reliability (EM and TDDB).

We examine the impact of line-edge roughness (LER) on the variability in the on-current and saturation threshold voltage of ultrascaled FinFET devices via quantum-mechanical transport simulation. We obtain a realistic model of LER by decomposing the LER into short-lambda and long-lambda fluctuations, and we consider their separate influences on device performance. We show that the long-lambda fluctuations lead to greater device variability than the short-lambda fluctuations, and we explain the difference between the two cases via the influence of fluctuating quantum confinement arising from the LER. Finally, we consider devices in which the long-lambda fluctuations of the two fin edges are correlated and demonstrate that this correlation significantly improves the variability. Thus, we show the continued need for fabrication technology either to reduce the amplitude of the long-lambda fluctuations or to ensure the long-lambda fluctuations between the sidewalls of ultrascaled FinFET devices are correlated.

An analytical model of parasitic capacitance in inserted-oxide FinFETs (iFinFETs) is proposed. A comparative study on the parasitic capacitance of contemporary multigate devices conforming to 7-nm technology node targets is presented. The proposed model is validated against 3-D Technology Computer-Aided Design (TCAD) simulations. Dependence of the iFinFET parasitic capacitance on device design parameters, such as the inserted-oxide thickness (T-iox) and inserted-oxide recess (T-rec), is shown using the proposed model and TCAD simulations.

Planar ultra-thin body and box (UTBB 1-3 ) fully depleted silicon on insulator (FDSOI) devices have many advantages for future low-cost energy-efficient applications. However, process steps for scaling to ultra-thin FDSOI devices can be difficult to control, and extrinsic resistance can hinder any performance improvement. In this paper, we present a novel planar U-channel UTBB FDSOI device that can alleviate these problems.

Variability in the transistor parameters play a significant role in CMOS scaling to nanometer feature sizes. New channel materials such as silicon-germanium for pFET at 32nm and beyond are useful because of higher mobility and lower threshold voltage. However, gate-induced drain leakage (GIDL) is dominant in the total leakage and the use of germanium (Ge) may introduce additional variability sources. In this work, pre-halo Ge pre-amorphization impant (PAI) effect on systematic and random variability of GIDL and its reduction is investigated. We report that the elimination of Ge PAI from the process flow reduces GIDL and the effect of systematic variations but increases the static random GIDL variations in planar transistors based on high-k metal gate technology. However, the random GIDL variation difference associated with Ge PAI may change for scaled supply voltages.