α-cristobalite (α-C) is a polymorph of silica, mainly found in space exploration and geochemistry research. Due to similar densities, α-C is often used as a proxy for amorphous SiO2, particularly in computer simulations of SiO2 surfaces and interfaces. However, little is known about the properties of α-C and its basic oxygen defects. Using density functional theory (DFT) simulations we provide a comprehensive report on the properties of perfect structure and oxygen vacancies in α-C. The calculated properties of α-C are compared with those of the better-characterized α-quartz (α-Q). Our results demonstrated that the positively charged O vacancy in α-C is most stable in the dimer configuration, in contrast to α-Q, which favors the puckered configuration. A back-projected configuration was also predicted in both polymorphs. We calculated the optical transition energies and isotropic hyperfine constants for O vacancies in both α-Q and α-C, and compared our findings with the results of previous studies and experiments. This work, thus, offers one of the first in-depth investigations of the properties of oxygen vacancies in α-C.

A simulation package for CNT memory cells is developed, based on computational modeling of both the mesoscopic structure of carbon nanotube films and the electrical conductivity of inter-CNT contacts. The developed package enables the modeling of various electrical measurements and identification of a range of operation conditions delivering desirable device characteristics. This approach opens the path for optimization of the CNT fabric to meet performance requirements.

Carbon nanotubes (CNTs) have many interesting properties that make them a focus of research in a wide range of technological applications. In CNT films, the bottleneck in charge transport is typically attributed to higher resistance at CNT junctions, leading to electrical transport characteristics that are quite different from individual CNTs. Previous simulations confirm this; however, a systematic study of transport across junctions is still lacking in the literature. Herein, density functional tight binding (DFTB) theory combined with the nonequilibrium Green's functions (NEGF) method is used to systematically calculate current across a range of CNT junctions. A random sampling approach is used to sample an extensive library of junction structures. The results demonstrate that the conductivity of CNT contacts depends on the overlap area between nanotubes and exponentially on the distances between the carbon atoms of the interacting CNTs. Two models based solely on the atomic positions of carbon atoms within the nanotubes are developed and evaluated: a simple equation using only the smallest C–C separation and a more sophisticated model using the positions of all C atoms. These junction current models can be used to predict transport in larger‐scale simulations where the CNT fabric structure is known.

We developed 16 Mb 1T1R NRAM integrating CNTs resistor elements into the intermediate wirings of 55 nm CMOS. Excellent reliabilities were proven by the retention test at 150 °C extrapolated for 100 kh and the endurance test of 1E6 cycles. The switching speed was realized for cell array at 200 ns. In addition, we successfully fabricated CNTs resistor elements with 49% shrunk small via pitch cell area and realized advantageous high switching speed with 0.5 ns single pulse even omitting verify operation.

Root-cause of instability in carbon nanotubes memristors is analyzed employing ultra-short pulse technique in combination with atomic-level material modeling. Separating various factors affecting switching operations allowed to identify structural features and operational conditions leading to improved cell characteristics.

A ultra-high purity carbon nanotube formulation and film is described. This material system has been successfully integrated into a semiconductor fabrication process for electronic device applications. Key challenges that were resolved to successfully implement this new material system into the semiconductor process are described.

Carbon nanotubes (CNT) resistance-change memory devices were assessed for neuromorphic applications under high frequency use conditions by employing the ultra-short (100 ps -10 ns) voltage pulse technique. Under properly selected operation conditions, CNTs demonstrate switching characteristics promising for various NN implementations.

Advanced memory technology based on carbon nanotubes (CNTs) (NRAM) possesses desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems for NRAM have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018-2023 (http://bccresearch.com/pressroom/ smc/bcc-research-predicts:-nram-(finally)-to-revolutionize-computer-memory). These opportunities are helping drive the realization of a shift from silicon-based to carbon-based (NRAM) memories. NRAM is a memory cell made up of an interlocking matrix of CNTs, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to moving electrons for traditional silicon-based memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

Advanced memory technology based on carbon nanotubes (NRAM) has been shown to possess desired properties for implementation in a host of integrated systems due to demonstrated advantages of its operation including high speed (Nanotubes can switch state in picoseconds), high endurance (over a trillion), and low power (with essential zero standby power). The applicable integrated systems have markets that will see compound annual growth rates (CAGR) of over 62% between 2018 and 2023, with an embedded systems CAGR of 115% in 2018 to 2023 [1]. These opportunities for NRAM technology are helping drive the realization of a shift from silicon to a carbon-based memory. NRAM is made up of an interlocking matrix of carbon nanotubes, either touching or slightly separated, leading to low or higher resistance states respectively. The small movement of atoms, as opposed to electrons for traditional memories, renders NRAM with a more robust endurance and high temperature retention/operation which, along with high speed/low power, is expected to blossom in this memory technology to be a disruptive replacement for the current status quo of DRAM (dynamic RAM), SRAM (static RAM), and NAND flash memories.

We present results of self-consistent electronic structure calculations for an electromechanical memory cell consisting of a carbon nanotube (CNT) fabric between titanium leads to elucidate the mechanism whereby the applied bias works to close the current gaps in the CNT fabric. We demonstrate that the asymmetry in the bias conditions required to achieve the "SET" operation of the cell (changing it from a high resistivity to low resistivity) results from the nature of a voltage drop in a compensated semiconducting material and depends sensitively on the background charge as well as on the position of the layer where the conducting gaps occur. The calculations provide insight into the behavior of the material and suggest possible fabrication strategies to modify the functionality. (C) 2016 The Japan Society of Applied Physics

In emerging non-volatile memories, nano-random access memory (NRAM) has advantages of small program current and high endurance compared with resistive RAM (ReRAM) and phase-change RAM (PRAM). This work comprehensively investigates NRAM set and reset program characteristics by measuring a 116nm 4 Mbit NRAM cell array. Specifically, reset is found more dependent on reset voltage than reset current. Next, NRAM set and reset bit error rates (BERs) have less significant reduction compared with the increased ratio of set and reset pulse widths. The reset BER can also be reduced by applying multiple reset pulses. Moreover, 108 write cycles are measured on 256 bytes NRAM cells, no wear-out or broken cell is found. Finally, the program characteristics of two verify-reset schemes are compared. The maximum verify-reset voltage can be reduced by increasing the number of reset pulses. (C) 2016 The Japan Society of Applied Physics

Carbon Nanotube (CNT) memory has a simple structure, low voltage, low current, and fast switching mechanism, and endurance up to 1012 cycles has been demonstrated [1]. In order to optimize set and reset algorithms and understand the mechanisms of CNT reliability, this work studies the CNT after 107 endurance cycles for different combinations of set and reset endurance voltages. It is confirmed that set and reset cycling voltages affect the count and ratio of set and reset errors after 107. Based on measurement of a 6Mb test chip, the endurance condition in which the set voltage is lower than the reset voltage, gives the best cycling.

A novel error correction scheme, called reset-check-reverse- flag (RCRF), is proposed to improve the reliability of storage class memories (SCMs). RCRF divides the conventional Bose-Chaudhuri-Hocquenghem (BCH) code length into multiple subsections. One flag bit is added to each subsection to correct program errors. By reversing the flag bit and user data, at least one reset error in each subsection can be recovered. A 4 Mbit carbon nanotube (CNT) based nano-random access memory (NRAM) cell array is measured to verify this scheme. During 10(8) write cycles, it is demonstrated that RCRF reduces the program bit error rate (BER) by 50% and only requires 0.4% extra array area for the flag bits. Next, BCH ECC is applied after RCRF to correct the remaining errors. Compared with the conventional BCH ECC-only approach, the proposed combination of RCRF and BCH ECC reduces parity overhead by 35% and ECC decoding latency by 16%. Therefore, RCRF is especially suited for read-intensive types of data storage, such as video and audio. On the other hand, for high endurance applications, RCRF and BCH ECC is also effective to improve the cycling reliability of resistive memories, and 50 times endurance extension is demonstrated for a 50 nm AlxOy resistive RAM (ReRAM) test chip.

A 4 M-bit carbon nanotube (CNT) based non-volatile memory (NRAM) cell array is measured to investigate program characteristics. In detail, first, reset is measured by controlling the program voltage and current independently. Reset is found mainly dependent on the program voltage rather than the program current. Next, 10 write cycles are applied to the memory cell array and no cell array wear-out or broken cell is found. Finally, program characteristics of two verify-reset schemes are compared. The maximum verify-reset voltage can be reduced by increasing the number of reset pulses.

Carbon nanotube (CNT)-based random access memory (NRAM) cells are measured to investigate cell program at different set current compliances and temperatures. Then, a physical model is proposed to explain the mechanism of cell resistance switching. Specifically, the changes in the NRAM cell tunneling current and resistance can be attributed to the variation of the distance between CNTs. An attraction force (F attraction ), generated by electrical induction, reduces the distance, whereas a repulsion force (F repulsion ), generated by phonon-induced temperature, increases the distance. It is proposed that the dominance of these two forces is reversed during set and reset programs, possibly due to the reduction of F repulsion in set program. Finally, two verify-reset schemes are proposed to improve the NRAM cell verify-program performance. The first proposal, multiple-pulse reset demonstrates 23% program time reduction by skipping a cell resistance read between two successive reset pulses. The second proposal, gate-pulse reset is calculated to decrease more than 40% program energy by reducing bitline charge energy in array program.