A stress-and-sense charge pumping (SSCP) technique is proposed in this paper to measure the stress-induced interface trap (ΔN it ) in real-time evolution without stress interruption. Results show that the ΔN it measured by this SSCP technique is much higher than that measured by the conventional method. This difference is resulted from the recovery induced by stress interruption during the sensing measurements. The ΔN it measured by SSCP method after interruption is approximately equal to that by the conventional one. The amount of recoverable ΔN it is almost constant and independent of permanent damage. The stress-induced threshold voltage shift (ΔV th ) and ΔN it under various stress frequencies and duty cycles are also measured. The ΔV th seems to depend only on the total stress time of stress pulse. The ΔN it measured by SSCP with different frequencies and duty cycles is similar. The ΔN it also depends on the total stress time of stress pulse, but not the off time during the nonstress half cycle. In addition, it is found that the recovery induced by nonstress half cycle of ac stress is almost negligible as compared with that induced by stress interruption. Moreover, a two-stage phenomenon is observed on ΔN it evolution. Results in this paper indicate that the stressing indeed induces trap generation in the first stage.

Ge MOS devices with about 95% Ge 4+ in HfGeO x interfacial layer are obtained by H 2 O plasma process together with in situ desorption before atomic layer deposition (ALD). The equivalent oxide thickness is scaled down to 0.39 nm; the leakage current is decreased as well. The improvement can be attributed to the in situ Ge suboxide desorption process in an ALD chamber at 370 °C. The interface trap density and frequency dispersion need further process development to be reduced.

High-k gated metal-oxide-semiconductor field-effect-transistors (MOSFETs) with Cl-2 and CF4 plasma treatments are studied in this work. A higher-k HfON with more tetragonal phase is formed by the halogen plasma treatment on interfacial layer (IL). A low inversion equivalent oxide thickness in MOSFET is obtained with the Cl-2 plasma treated IL In addition, high mobility and transconductance, and low subthreshold swing are obtained by the Cl-2 plasma treatment, which therefore is a promising interface engineering for advanced MOSFETs. (C) 2014 Elsevier Ltd. All rights reserved.

To better understand the channel-hot-carrier (CHC)-induced reliability problems, a modified charge-pumping (CP) technique is proposed to characterize the distribution profiles of trap generation in MOSFETs with high- k gate-stack. The effects of gate leakage current on CP measurements were minimized to ensure the correct CP data. While applying dynamic drain bias, the gate-induced drain leakage current is also considered to get correct CP data. Through the CP with dynamic drain bias and various gate pulse frequencies, the profiling of CHC stress-induced interface- and border-traps can be achieved. The CHC stress-induced interface trap generation appears along whole the channel but that-induced border trap generation is mainly located above the pinchoff region near the drain and decreases dramatically toward the center of the channel. Thus, the CHC stress causes quite localized border trap generation at the gate-edge region inside the high- k dielectric. The reliability data measured by CP with different gate voltage swings confirm that CHC stress causes interface trap generation through whole the channel and significant border trap generation at gate-edge region.

The equivalent oxide thickness in Ge MOS device is scaled down to 0.39 nm, and the leakage current is decreased as well. The improvement can be attributed to the in-situ Ge sub-oxide desorption process in an ALD chamber at 370 ° C. About 95% Ge 4+ in HfGeO x interfacial layer are obtained by H 2 O plasma process together with in-situ desorption before atomic layer deposition.

A junctionless (JL) polycrystalline-based flash memory device with HfO 2 /Si 3 N 4 (HN) stacked trapping layer is studied for the first time. Effects of the HN stacked trapping layer on JL and inversion-mode (IM) flash devices are compared. JL device shows faster programming speed than the IM one because of its heavily doped n-channel. Specially, comparable erasing speed of JL device can be achieved by HN stacked trapping layer due to more effective electron detrapping. JL device with HN stacked trapping layer also shows better retention characteristics and keeps a larger window after 10 5 programming/erasing cycles, which makes it promising for 3-D memory integration in the future.

Display Omitted We study the high-k dielectrics with in situ NH3, N2, H2 plasma treatment.EOT and Jg are reduced for the MOS device with NH3 plasma treated HfO2.A tetragonal phase HfO2 is obtained for the MOS device with NH3 plasma treatment.Stress induced Vfb shift and leakage are reduced for NH3 plasma treated HfO2.In-situ NH3 plasma treatment in ALD is a promising technique for high-k process. Metal oxide semiconductor (MOS) devices with in situ remote plasma treatment during high-k dielectric deposition are studied in this work. The EOT value and leakage current of the MOS device with in situ NH3 plasma treated high-k dielectrics can be significantly reduced to 0.83nm and 1.7í¿10-3A/cm2, respectively. The stress-induced flat-band voltage shifts and leakage current are obviously reduced as well. In-situ remote plasma treatment also provides a good approach of nitridation for high-k dielectrics. The oxygen vacancy can be passivated by nitrogen, which suppresses further oxygen diffusion and the formation of the oxygen vacancies. The in situ NH3 plasma treatment is useful for high performance MOS devices with good reliability.

The TaN/HfON/GeO2/n-Ge pMOSFETs were fabricated with different formation processes of GeO2 interfacial layer. Ultra low EOT of around 0.5 nm is achieved using GeO2 grown by H2O plasma together with in-situ grown HfON gate dielectric, and simultaneously the peak hole mobility of Ge pMOSFET is 312 cm2/V*s.

P-channel charge-trapping flash memory devices with Si, SiGe, and Si/Ge super-lattice channel are investigated in this work. A Si/Ge super-lattice structure with extremely low roughness and good crystal structure is obtained by precisely controlling the epitaxy thickness of Ge layer. Both programming and erasing (P/E) speeds are significantly improved by employing this Si/Ge super-lattice channel. Moreover, satisfactory retention and excellent endurance characteristics up to 106 P/E cycles with 3.8V memory window show that the degradation on reliability properties is negligible when super-lattice channel is introduced.

Effects of HfO2/Si3N4 bandgap-engineered trapping layer (BETL) on poly-Si flash memory device are studied for the first time. Planar and nanowire (NW) channel flash memory devices are successfully fabricated to study the effects of BETL. The programming and erasing speeds can be improved by BETL on both planar and NW channel devices, and the improvement is more obvious on NW channel devices with even a lower operation voltage. The device with BETL and NW channel demonstrates the best programming and erasing speeds due to the electric-field enhancement effect and the band-engineering in charge-trapping layer. It also shows good retention and endurance properties, which makes it promising for 3-D memory integration. (C) 2013 Elsevier B.V. All rights reserved.

Operation characteristics of p-channel TaN/Al2O3/HfO2/HfAlO2/SiO2/Si MAHOS-type nonvolatile memory devices with an epitaxial Si/Ge super-lattice (SL) channel are investigated in this letter, where the SL channel is characterized with good crystal structure and high thermal stability. Remarkable improvement on programming and erasing speeds is observed, as compared to those with SiGe channel. Furthermore, the degradation on reliability properties of retention and endurance is negligible for the device with employing a SL channel.

For better performance on charge-trapping (CT) flash device, tunneling layer stacks of nitrogen (N)-rich SiN/SiO2 and low temperature (LT) N-rich SiN/SiO2 are studied. The programming and erasing speeds of CT flash device are significantly improved by the tunneling layer stacks due to the lower conduction and valence band offsets of N-rich and LT N-rich SIN, but worse retention is observed with the lower offsets. The effects of tunneling layer stacks on devices with silicon (Si)-rich SIN trapping layer are also studied. The programming and erasing speeds can be both improved due to its smaller bandgap. When stacked tunneling layers are applied to devices with Si-rich SiN trapping layer, their programming speeds are almost the same as those of devices with single tunneling layer. Only erasing speeds are improved by tunneling layer stacks. The retention properties of CT flash devices with Si-rich SiN trapping layer are not as good as those with standard one. (C) 2012 Elsevier Ltd. All rights reserved.

The operation characteristics of p-channel TaN/ Al 2 O 3 /HfO 2 /HfAlO 2 /SiO 2 /Si MAHOS-type nonvolatile memory devices with different Ge contents in a SiGe buried channel are investigated in this letter. Compared with those of a device having a conventional Si-channel, both programming and erasing speeds are significantly improved by employing a Si 0.7 Ge 0.3 buried channel. Satisfactory retention and excellent endurance characteristics up to 10 6 P/E cycles with 4.1-V memory window show that the degradation on reliability properties, if it exists, is negligible when the SiGe buried channel is introduced.

Since the SiGe or Ge channel materials are desirable to enhance the carrier mobility degraded by ultrathin high-k gate dielectric, the pMOSFET device with novel superlattice (SL) SiGe channels is proposed in this letter. Experimental results show that the electrical characteristics of MOSFET can be obviously improved by an SL virtual substrate. The peak hole mobility of the pMOSFET device with SL is enhanced by about 100% as compared to that with the Si one. The on-off ratio of the Id-Vg curve is beyond eight orders, and the electrical thickness in inversion (Tinv) value of the gate dielectric can be ~1.4 nm. The source/drain activation temperature of 650°C is particularly suitable to high-k dielectric process.

A stacked Si 3 N 4 /HfO 2 charge-trapping (CT) layer was proposed to improve erase operation and retention for CT nonvolatile memory (NVM) devices. The improvement can be attributed to the smaller valence band offset of Si 3 N 4 to Si and the higher barrier for electron detrapping from HfO 2 to Si 3 N 4 . The programming and retention characteristics of CT NVM devices can be further enhanced by inserting Al 2 O 3 between Si 3 N 4 and HfO 2 as the CT layer. This is because most of the injecting charges are trapped at the Si 3 N 4 /Al 2 O 3 interface, and Al 2 O 3 also provides a high barrier for electron detrapping.

Metal oxide semiconductor field effect transistors (MOSFET) with SiGe channel and higher-k gate dielectric are studied in this work. Samples with TaON/HfO2 or TiON/HfO2 stacks show larger drain current, better transconductance, and smaller subthreshold swing than that with single HfO2 layer. In addition, the reliability for SiGe pMOSFET device is clearly improved with TaON/HfO2 stacks in terms of degradation of Gm and Vth after hot-carrier stress. The integration of SiGe channel with TaON higher-k dielectric is useful for high performance pMOSFETs. (C) 2012 Elsevier Ltd. All rights reserved.

A tetragonal HfO2 (t-HfO2) with higher-k value and large band gap is investigated in this work. X-ray diffraction analysis shows a t-HfO2 can be formed by using Cl2 plasma treatment at the HfO2/Si interface after a post deposition annealing at 650 °C. The mechanisms of t-HfO2 formation can be attributed to the Si diffusion and oxygen vacancy generation which are formed by Cl2 plasma treatment. From the cross-sectional transmission electron microscope and capacitance-voltage measurement, the k value of this t-HfO2 is estimated to be about 35. The optical band gap value for t-HfO2 is similar to that of the monoclinic.

The effects of interfacial layer at high-k dielectric/Si substrate formed by using stress-relieved pre-oxide (SRPO) treatment on electrical characteristics of MOS devices were studied in this work. The equivalent oxide thickness value could be scaled with reducing the thickness of the high quality IL. The reliability in terms of stress-induced leakage and stress-induced Vfb shift is clearly improved for MOS device with a SRPO treatment. Besides, the constant-voltage stress-induced interface trap generation in MOSFET was measured by charge-pumping techniques. The influences of stress and recovery on devices with HfO2 high-k dielectric are also compared. Results show that the stress induced Vth shifts can be separated into two stages, namely, trap filling and generation. The trap generation stage is only determined by the stress voltage and temperature.

P-channel charge-trapping flash transistor devices with different Ge contents in SiGe channel and different thicknesses of Si0.8Ge0.2 channel are investigated in this work. Both programming and erasing speeds are significantly improved by employing SiGe channel in comparison with those employing Si-channel. Moreover, satisfactory retention and endurance characteristics for device with SiGe channel are also achieved, which indicates the out-diffusion of Ge atoms from channel does not affect the reliability properties of flash memory devices.