Fully-additive printed electronics enables low-cost and flexible circuit fabrication, but severe process variations significantly degrade device uniformity and modeling accuracy. This work presents an AI-assisted modeling framework for flexible thin-film transistors (TFTs) fabricated via a fully-additive printed electronics process. To accurately capture the nonlinear current voltage characteristics of the printed transistors, a hybrid AI-assisted model is proposed, combining a physics-based trend equation with a residual neural network (RNN). The trend model provides a physically interpretable baseline describing the device’s general behavior, while the RNN learns the fine-grained residuals from experimental data. A physics-informed loss function is further incorporated to enforce smoothness and monotonicity, ensuring that the model adheres to fundamental device physics. Experimental validation on printed flexible FETs demonstrates that the proposed approach achieves high prediction accuracy and physical consistency across wide bias ranges and different bending conditions.

Voltage-controlled oscillator-based analog-to-digital converters (VCO-ADCs) inherently exhibit a sinc filtering response that serves as an intrinsic anti-aliasing filter (AAF) for attenuating out-of-band signals. However, the filter attenuation, even for a second-order (sinc(2)) response in the state-of-the-art VCO-ADC, is inadequate to sufficiently suppress aliased signals below the noise floor in wideband (>= 100 MHz) RF receiver systems. This necessitates power and area-consuming dedicated analog AAFs, incongruous for low-power IoT applications. In this paper, we propose a novel RF VCO-ADC architecture with an unprecedented intrinsic quasi-sinc(3) AAF. The ADC embodies a proposed opposite-phase sampling technique that emulates a finite-impulse-response filter, effectively enhancing the inherent sinc AAF by two orders, yet featuring low complexity. The proposed ADC is designed in a CMOS 65 nm process and simulated for comparison against state-of-the-art ADCs. On the basis of this comparison, the proposed ADC achieves a significant 20 dB improvement in maximum alias attenuation at the sampling frequency without requiring extra AAFs, outperforming the state-of-the-art with a 6th-order analog AAF. It dissipates only 0.34 mW, similar to 4x lower than the state-of-the-art, and features exceptional energy efficiency with a highly competitive Figure-of-Merit of similar to 34 fJ/conversion, similar to 2x more efficient than the state-of-the-art.

Due to ever-increasing demand for high-level integration, low power dissipation and high fidelity, Class D amplifier ICs (CDA ICs) need to feature very high power supply rejection ratio (PSRR), very low total harmonic distortion plus noise (THD+ N), low output noise, high power-efficiency, low electromagnetic interference (EMI), and fixed switching frequency. We propose a fully integrated filterless CDA IC embodying a novel loop-filter that simultaneously features an ultrahigh loop gain of>200 dB and high carrier attenuation of -10 dB. Due to the ultrahigh loop gain and high carrier attenuation, the linearity and PSRR of the CDA IC is significantly improved. The proposed CDA IC further embodies a novel deadtime circuit that can eliminate the false switching in the Class D output stage, hence reducing the EMI and further improving the linearity of the CDA IC. The proposed CDA IC simultaneously features an ultrahigh PSRR (>100 dB from 100 Hz to 1 kHz), very low THD + N (0.005%), very low output noise (16 mu V), and low EMI (10 dB below the EN55022 Class B standard)-yet with fixed switching frequency (400 kHz). When benchmarked against state-of-the-art designs, our CDA IC features the highest PSRR, allowing hookup directly to the battery and features the lowest output noise.

Contemporary digital circuits are synchronous-logic and are operationally error-free because they are designed to complete their operation within a predefined time period. In some applications, such as the MOST operating in ultra-deep subthreshold or in flexible electronics where the TFT is printed, the ensuing operation of digital circuits is prone to error. This is because the variations of the delay of the transistor are very high and the ensuing predefined time period is difficult to ascertain. In the case of the printed TFT where its substrate is flexible and hence possibly bent, the delay is possibly intractable, in part because the profile of the bending may not be known. In this paper, we will discuss the commonality between ultra-deep subthreshold and printed TFTs in terms of their variations. We describe the application of the esoteric asynchronous-logic Quasi-Delay-Insensitive (QDI) signaling protocol to design digital circuits that innately accommodate intractable delay characteristics, i.e., error-free operation despite intractable variations. To mitigate the hardware, power and timing overheads of QDI, we will present our proposed modified signaling protocol named Pseudo-QDI and our proposed Pre-Charged-Static-Logic design style.

The envelope tracking (ET) design methodology is routinely adopted to improve the efficiency of radio frequency power amplifiers (PAs). One short coming of state-of-the-art ETPAs is that their supply modulators are usually designed and optimized for a single communications standard. They are either incompatible in modern communication devices where multiple communications standards are used, and/or the efficiency unoptimized when the devices operate in standards other than the designed standard. To circumvent this shortcoming, a novel supply modulator for multistandard communications is proposed. The proposed design embodies a proposed dual-mode Sigma-Delta control block and an adaptive biasing Class AB amplifier, which allows the supply modulator self-adjusting its operation and optimizing the efficiency according to the application. A prototype supply modulator IC is designed and fabricated using a 180 nm CMOS process. Based on measurements, the proposed supply modulator features the highest static efficiency of 91% and the highest 3 dB backoff static and dynamic efficiency compared to the state-of-the-art supply modulators. When tracking 40 MHz LTE-A envelope signals, the prototype supply modulator achieves a high efficiency of 85% at 1.8 W output power, and the efficiency remains high >80% for a wide range of output power, from 0.5 to 1.8 W.

The low carrier mobility of (printed) semiconductors and high variations of the printed/flexible electronic elements are some of the most difficult challenges for the practical realization of complex printed/flexible electronic circuits. Although contemporary circuit designs accommodate some degree of process variations in conventional silicon processes largely by negative feedback, negative feedback is largely inapplicable in printed/flexible electronics. This is because the gain of the transistors is too low in electronic circuits to realize high open-loop gain, but also because negative feedback is inapplicable to digital circuits in the traditional sense. In this paper, we describe the co-design between the first three supply chains of Printed/Flexible Electronics – the co-design between our modified semiconductor, Fully-Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics printing process and a process-variation-tolerant digital circuit design methodology. The first two co-design supply chains pertain to a low-cost screen-printing process while the last co-design chain pertains to the Quasi-Delay-Insensitive asynchronous-logic digital design methodology (vis-à-vis synchronous-logic) that is self-timed, hence virtually tolerant to any variations. We will also delineate our measurements on digital circuit based on codesign of the aforesaid supply chains, depicting the merits of our modified semiconductor, low-variation printing process, and the ensuing functional printed digital circuit.

Sensing and its electronics based on printed/flexible electronics offer unique attributes of mechanical flexibility of its substrate, hence the unique applications. Nevertheless, one of the ensuing key challenges of flexible-electronics-based sensing is the issues associated with consistency and repeatability of its parameters of the flexible electronics elements/sensors due to their variations, which are sometimes intractable. These may be due to manufacturing variations, aging, when the substrate is bent, and so on. In this article, we describe our codesign between the different chains of the flexible electronics supply chain to derive practically flexible electronics and sensors for applications where the substrate is expected to bend, e.g., in an augmented sensing e-skin smart glove application. This effort includes our fully additive low-temperature all-air low-cost screen printing process, and how we obtain consistency and repeatability. To improve the matching of thin-film transistors-a critical consideration for conditioning sensor outputs-we describe layout techniques where relatively good matching can be achieved, but with area overheads. We describe how we accommodate the variations of printed elements and circuits embodying printed elements when the substrate is bent-a self-compensating means-and propose the application of the same for printed sensors. The cost of our self-compensation means is without power or area overheads, albeit more (uncomplicated) printing steps. We finally describe our process development kit (PDK) encompassing all of the aforesaid to predict the performance of the printed circuits and sensors, including the effects of bending and our proposed self-compensation thereto. We demonstrate the efficacy of our methods based on measurements on printed elements and circuits.

Flexible Hybrid Electronics (FHE), heterogeneous electronics embodying both conventional silicon electronics and printed electronics, is an emerging technology with huge market potential as it is advantageous compared to conventional silicon electronics and the emerging Printed Electronics - FHE features better mechanical flexibility/conformability and lower cost compared to conventional silicon electronics, and higher performance compared to Printed Electronics. In this paper, a comprehensive literature view on FHE is provided, including the state-of-the-art FHE development, FHE supply chains, and design challenges.

We propose a circuit that performs a reverse current reduction (RCR) in switched-mode dc-dc converters. The reverse current is undesirable since it causes power losses when the converter is operating in the Discontinuous Conduction Mode (light-load currents). Conventional designs for reducing the reverse current often require an accurate comparator or complex circuitries to sense and reduce the reverse current. The RCR circuit is simple, and relaxes the accuracy requirements for the comparator since the RCR circuit senses the reverse current differentially. Power transistors operating at 3.3 V input, 2 V output, 23 mA output (DCM operation), 5 MHz switching frequency, and combined with the RCR circuit are simulated using a 0.18 pm CMOS process. The RCR circuit reduces the reverse current of the power transistors by 83% and that translates to an improvement of the power efficiency by 16% when compared to that achieved by the same power transistors but with a conventional reverse-current reduction circuit.

We describe a supply modulator comprising a proposed delay-based hysteresis controller, proposed wideband classAB amplifier, and class-D amplifier for an envelope tracking (ET) power amplifier (PA). We investigate the power dissipation and optimization method of the supply modulator for wideband applications taking into consideration the propagation delay, and show that a controller with zero threshold current not only improves the bandwidth of the supply modulator but also reduces its power dissipation. Based on our investigations, we propose a delay-based hysteresis controller embodying a novel high-speed current comparator whose reference current (threshold current) is zero, thereby achieving higher power-efficiency and simpler hardware. We further propose a class-AB amplifier, which features a high bandwidth and accurately controlled quiescent current. The proposed supply modulator features simultaneously the wide bandwidth (40 MHz), high output power (2.5 W), high peak efficiency (91%), high output voltage swing (3 V), and low output ripple noise (4 mV(rms)) at 3.6-V supply. The ET PA embodying our proposed supply modulator achieves a high power-efficiency of 41.4% at 28.5-dBm peak output power and 34.4% at 3-dB backoff-a significant >1.6 x improvement over the radio frequency PA without the supply modulator.

Despite the huge market potential of Printed Electronics on Flexible substrates, the printed circuits and systems are yet to be manufacturable due to high cost fabrication processes, large process variations between devices, large and somewhat intractable variations when the devices and their substrates are bent, and lack of a comprehensive Process Development Kit (PDK). In this review paper, we review our Low-Cost Fully-Additive printing process with these four shortcomings addressed. To the best of our knowledge, this process is arguably the Fully-Additive printing process that is closest to being manufacturable and for the realization of practical intelligent printed electronics.

Despite the gargantuan market potential, Printed Electronics-only (PE-only) circuits and systems on flexible substrate remain nascent. There are a number of reasons for this, including the inavailability of Process Development Kits (PDKs) to facilitate PE circuits and systems design and to predict manufacturability (due to the innately high process variations of PE). In this paper, we describe an "Open-Platform" PDK for our Fully-Additive Low-Temperature All-Air printing process with Very Low Process Variations. Our PDK embodies a novel simple yet accurate transistor model that can not only accurately model the printed transistors depending on their layout and when they are flat (unbent substrate) but also accurately model the process variations when they are bent (bent substrate). This PDK for bending is important for PE circuits and systems whose substrate is adhered to uneven surfaces or bent to fit odd spaces, thereby expanding the applicability of PE circuits and systems. The efficacy of the Open-Platform and the proposed PE transistor model is verified by means of comparisons between simulations and measurements of basic individual printed electronic elements and for several fundamental printed digital and analog circuits. These comparisons include when the substrate is flat and bent, depicting that bending is not only detrimental, but may conversely be advantageously exploited. The proposed PDK is compatible with commercial computer aided design simulation tools.

We have established new methodologies, materials, processing, devices, and circuits for integrating III-V devices monolithically into CMOS circuits. Certain constraints were applied on this research from the start in order to converge on viable commercial strategies as the research moves closer to a path for new innovation in the semiconductor industry. Integration technology has been established for incorporating HEMTs and LEDs into CMOS integrated circuits, and both nitride-based and arsenic-phosphide-based materials are currently supported. Device models are inserted into standard foundry design libraries, allowing silicon technology efficiencies such as exploring various circuit designs before final physical silicon and fabrication-test feedback loops using test chip designs.

Due to ever-increasing demand for high-level integration, high system (mechanical) flexibility, small form factor, and/or thermal conductivity, the integrated circuits (ICs) need to be thin, preferably <;200μm. One potential drawback of thin IC is that the efficiency of the RF transformer may be degraded, hence resulting in reduced overall system efficiency and increased power dissipation. In this paper, the effects of substrate thickness of the ICs on transformer performance are analyzed. A fully symmetrical interleaved transformer is designed and simulated based on CMOS 65nm process and the analyses herein are based on the 3D Lumped substrate model. We show that the efficiency of the transformer remains largely uncompromised when the substrate thickness is >50μm and reduced by ~28.6% (from 0.7 to 0.5) at 2GHz when the substrate thickness is reduced to an ultra-thin 10μm. The results herein provide a guideline for optimization of substrate thickness without affecting the performance of transformer.

Printed/Organic Electronics (PE) is an emerging technology with gargantuan market potential, particularly if its realization is low cost and the supply chain associated with its design is manageable/established. For the former, a Fully-Additive All-Air Low-Temperature process (vis-à-vis a Subtractive process) is desirable, while for the latter, a comprehensive Process Development Kit (PDK) for Electronic Design Automation tools is necessary. In this paper, we delineate, arguably the first-ever PDK for PE - this PDK is developed for our Fully-Additive All-Air Low-Temperature printing process with very-low process variations, and capable of complete circuit realizations on a myriad of substrates, including low-cost low-temperature flexible plastic films. Our proposed PDK embodies accurate modeling of the printed transistor and printed passive elements. With these models, comprehensive schematic simulations can be performed, including Monte Carlo simulations. We demonstrate the efficacy of our PDK, in part based on our measured process variations. The layout design rules for our Fully-Additive printing process to facilitate layout design - imperative for estimating the printing area and the printing cost - are also delineated herein.

Class D amplifiers (CDAs) are increasingly ubiquitous as the audio power amplifier (loudspeaker driver) in audio devices due to their significantly higher power-efficiency compared to their linear counterparts. In this paper, a comprehensive review on the design of audio Class D amplifiers is provided, including a comparison of commonly used design architectures/modulation schemes. The key design parameters, including Total Harmonic Distortion, Power Supply Rejection Ratio, Intermodulation Distortion, are discussed and the design tradeoffs between these parameters delineated.