Due to ever-increasing demand for high-level integration, low power dissipation and high fidelity, Class D amplifier ICs (CDA ICs) need to feature very high power supply rejection ratio (PSRR), very low total harmonic distortion plus noise (THD+ N), low output noise, high power-efficiency, low electromagnetic interference (EMI), and fixed switching frequency. We propose a fully integrated filterless CDA IC embodying a novel loop-filter that simultaneously features an ultrahigh loop gain of>200 dB and high carrier attenuation of -10 dB. Due to the ultrahigh loop gain and high carrier attenuation, the linearity and PSRR of the CDA IC is significantly improved. The proposed CDA IC further embodies a novel deadtime circuit that can eliminate the false switching in the Class D output stage, hence reducing the EMI and further improving the linearity of the CDA IC. The proposed CDA IC simultaneously features an ultrahigh PSRR (>100 dB from 100 Hz to 1 kHz), very low THD + N (0.005%), very low output noise (16 mu V), and low EMI (10 dB below the EN55022 Class B standard)-yet with fixed switching frequency (400 kHz). When benchmarked against state-of-the-art designs, our CDA IC features the highest PSRR, allowing hookup directly to the battery and features the lowest output noise.

The envelope tracking (ET) design methodology is routinely adopted to improve the efficiency of radio frequency power amplifiers (PAs). One short coming of state-of-the-art ETPAs is that their supply modulators are usually designed and optimized for a single communications standard. They are either incompatible in modern communication devices where multiple communications standards are used, and/or the efficiency unoptimized when the devices operate in standards other than the designed standard. To circumvent this shortcoming, a novel supply modulator for multistandard communications is proposed. The proposed design embodies a proposed dual-mode Sigma-Delta control block and an adaptive biasing Class AB amplifier, which allows the supply modulator self-adjusting its operation and optimizing the efficiency according to the application. A prototype supply modulator IC is designed and fabricated using a 180 nm CMOS process. Based on measurements, the proposed supply modulator features the highest static efficiency of 91% and the highest 3 dB backoff static and dynamic efficiency compared to the state-of-the-art supply modulators. When tracking 40 MHz LTE-A envelope signals, the prototype supply modulator achieves a high efficiency of 85% at 1.8 W output power, and the efficiency remains high >80% for a wide range of output power, from 0.5 to 1.8 W.

We describe a supply modulator comprising a proposed delay-based hysteresis controller, proposed wideband classAB amplifier, and class-D amplifier for an envelope tracking (ET) power amplifier (PA). We investigate the power dissipation and optimization method of the supply modulator for wideband applications taking into consideration the propagation delay, and show that a controller with zero threshold current not only improves the bandwidth of the supply modulator but also reduces its power dissipation. Based on our investigations, we propose a delay-based hysteresis controller embodying a novel high-speed current comparator whose reference current (threshold current) is zero, thereby achieving higher power-efficiency and simpler hardware. We further propose a class-AB amplifier, which features a high bandwidth and accurately controlled quiescent current. The proposed supply modulator features simultaneously the wide bandwidth (40 MHz), high output power (2.5 W), high peak efficiency (91%), high output voltage swing (3 V), and low output ripple noise (4 mV(rms)) at 3.6-V supply. The ET PA embodying our proposed supply modulator achieves a high power-efficiency of 41.4% at 28.5-dBm peak output power and 34.4% at 3-dB backoff-a significant >1.6 x improvement over the radio frequency PA without the supply modulator.

The Electroluminescent (EL) panel is an emerging backplane lighting technology and becoming increasingly popular in advertising display and facade decoration. Despite the increased popularity of the EL panel, driver circuit for large EL panel is nascent in part because of the required high output power. In this paper, a novel high power EL driver IC based on the emerging LEES-SMART GaN-on-CMOS process are presented and we show that this integrated class-D EL driver is advantageous compared to EL driver IC based on state-of-the-art silicon IC process.

The RF power amplifier (PA) is often the most power dissipative block in a smartphone and it usually dissipates ∼50% of the total power. One major drawback of the envelop tracking (ET) PA is the limited (and insufficient) bandwidth of its supply modulator. The emerging LEES-SMART InGaAs-on-CMOS process offers a higher operation speed (due to the high speed InGaAs transistors) and the capability for complex signal processing. In this paper, we present the fundamentals and design challenges of ET PA, and how the emerging LEES-SMART InGaAs-on-CMOS process may be exploited for a high power-efficiency.

One of the shortcomings of a number of Class D amplifiers (CDAs) designs is their susceptibility to supply noise, quantified by Power Supply Rejection Ratio (PSRR). Reported investigations thereto to-date remain incomplete/over-simplified, particularly the assumption that the AC ground is noise-less and a simplified fully-differential integrator model. In this paper, the effect of supply noise in the AC ground to PSRR is analytically investigated, and the associated analytical expressions derived. Of specific interest, the analysis is applied to the ubiquitous 3-state Bridge-tied-load (BTL) closed-loop PWM CDA, taking into consideration not only the effect of the non-ideal AC ground, but also the effect of the resistor and capacitor mismatch based on a realistic fully-differential integrator model. Further, the PSRR analysis of 3-state BTL closed-loop CDAs has to date been limited to the single-feedback topology and in this paper, extended to the double-feedback topology. These analyses and derived equations herein are useful as they provide valuable insights to CDA designers into the PSRR mechanisms—for example, the counter-intuitive observation that the CDA with 1st-order integrators provides similar or better PSRR than the CDA with 2nd-order integrators if both CDAs are designed to the same carrier attenuation—including the effect of various circuit parameters, and ensuing trade-offs. The derived analytical expressions are verified by means of HSPICE simulations and on the basis of practical measurements on discretely-realized CDAs.

Although class D amplifiers (CDAs) are highly advantageous over their linear amplifier counterparts in terms of power efficiency, their power efficiency remains undesirably low at nominal operation conditions where the output power is ~26 dB lower than its peak output power (due to the large crest factor of the audio/speech signal and headroom for adjustment). This is particularly the case for power-critical micropower applications such as hearing instruments. At nominal conditions, we find that the overcurrent protection circuit (for the output stage) is unexpectedly the most power-dissipative block in micropower CDAs. In this brief, we propose a novel ultralow-power overcurrent protection circuit, which features 67% lower power dissipation compared to conventional overcurrent protection circuit without compromising the IC area. To further verify the advantages of the proposed overcurrent protection circuit, an ultralow-power bang-bang CDA is designed. We show that, by employing the proposed overcurrent protection circuit, the power efficiency of the bang-bang CDA is significantly improved from 10.5% to 23.7% for a 64-Ω load and from 1.8% to 4.7% for a 400-Ω load.

Of the reported modulation techniques for Class D amplifiers (CDAs), CDAs based on Bang-Bang control modulation are arguably the most advantageous in terms of power-efficiency for low-power power-critical applications. To date, only single-ended and 2-state Bang-Bang control CDAs have been reported, and are hence disadvantageous because they require a bulky and costly output lowpass filter. In this paper, we propose the first-ever 3-state Bang-Bang control filterless CDA applicable to regular-power and ultra-low-power applications. Compared to other filterless 3-state CDAs, the proposed filterless 3-state Bang-Bang control CDA features the simplest hardware and the highest power-efficiency, but with somewhat compromised fidelity. Nevertheless, the fidelity thereto is sufficient for typical ultra-low-power applications such as low-to-mid performance wearable devices.

Class D amplifiers are ubiquitous as audio amplifiers due to their significantly higher power-efficiency compared to their linear counterparts (such as Class AB) due to the digital-like switching mode operation of the Class D output stage. However, one drawback of Class D amplifiers is the susceptibility to supply noise, qualified and quantified by Power Supply Rejection Ratio (PSRR) and Power Supply Induced Intermodulation Distortion (PS-IMD). In this paper, PSRR and PS-IMD of Single-ended, 2-state bridge-tied load (BTL) and 3-state BTL Class D amplifiers based on various carrier generators are investigated and compared. We show that the design of the carrier generator is critical and should be designed according to the structure of the Class D amplifier - we show in this paper that the same Carrier Generator may result in a high >70dB PSRR in a 3-state BTL Class D amplifier but an unacceptable 1dB PSRR in a 2-state BTL Class D amplifier. The investigation and comparison provide Class D amplifier designers useful insight on design and optimization of PSRR and PS-IMD.

Present-day smartphones and tablets demand high audio fidelity (e. g., total harmonic distortion + noise, THD + N << 0.01%), and high noise immunity (e. g., power supply rejection ratio, PSRR >> 80 dB) to allow high integration in an SoC. The design of conventional closed-loop pulse width modulation (PWM) Class-D amplifiers (CDAs) typically involves undesirable trade-offs between fidelity (qualified by THD + N), PSRR and switching frequency. In this paper, we propose a fully integrated CMOS CDA that embodies a novel input-modulated carrier generator and a novel phase-error-free PWM modulator, collectively allowing the employment of high loop-gain to achieve high PSRR, yet without compromising linearity/dynamic-range or resorting to high switching frequency. The prototype CDA, realized in 65 nm CMOS, achieves a THD + N of 0.0027% and a power efficiency of 94% when delivering 500 mW to an 8 Omega load from V-DD = 3.6 V. The PSRR of the prototype CDA is very high, -101 dB @217 Hz and 90 dB @1 kHz, arguably the highest to-date. Furthermore, the switching frequency of the prototype CDA varies from similar to 320 to 420 kHz, potentially reducing the EMI due to spread-spectrum. In addition, the prototype CDA is versatile with a large operating-voltage range, with V ranging from rechargeable 1.2 V single battery to standard 3.6 V smart-device supply voltages.

Audio Class D amplifiers (CDAs) based on bang-bang architecture are arguably the most power efficient architecture of all CDAs reported to-date due to their sheer hardware simplicity. At this juncture, the intermodulation distortion (IMD), an imperative measure that defines fidelity, remains unreported for bang-bang CDAs. In this paper, we investigate the mechanisms of and circuit parameters affecting the IMD of bang-bang CDAs. An interesting phenomenon is that the even-order IMD which is usually negligible/unreported in other CDAs and linear amplifiers may be higher than odd-order IMD therein. We derive analytical expressions for the IMD of the ideal and practical bang-bang CDAs, and the derived expressions are verified against HSPICE simulations and on the basis of measurements on a physical bang-bang CDA. These derived analytical expressions are useful as they provide valuable insights to the design of bang-bang CDAs and how parameters can be tradedoff to improve the IMD.

Conventional analog Pulse-Width-Modulation (PWM) Class D Amplifiers (CDAs) require analog input signals that are typically provided by a Digital-to-Analog Converter (DAC). A PWM-in PWM-out CDA, on the contrary, is able to receive digital PWM signals as its input signals, hence not requiring said DAC as the `interface' to digital signal processing circuits. In this paper, we analytically investigate the distortion and the noise-immunity (qualified by Power Supply Rejection Ratio, PSRR) of a PWM-in PWM-out CDA. Interestingly, we find that, contrary to conventional CDAs, the PWM-in PWM-out CDA features zero intrinsic distortions, and its PSRR is largely independent of the gain of the embodied integrator and is instead dependent on the switching frequency. The derived analytical expressions are afterwards verified on the basis of simulations of a practical PWM-in PWM-out CDA. In addition, the comparison between the said CDA and a conventional CDA demonstrates that the PWM-in PWM-out CDA is superior both in terms of Total-Harmonic-Distortion and PSRR.

Class D amplifiers are routinely employed in power-critical hearing aids for their high power-efficiencies, typically ~90% at high modulation indexes. Nevertheless, at the nominal operation condition where the modulation index M=0.1, the power-efficiency is typically 32%. In this paper, we show that the comparator embodied in the over-current protection circuit of the Class D output stage is dominant at M=0.1. We propose the design of a novel comparator (with performance parameters comparable with conventional comparators) featuring ~40% lower power dissipation. This improved lower power dissipation translates to a worthwhile 12% improvement in the power-efficiency of the Class D amplifier output stage. The proposed design herein is verified by computer simulations.

Open-Loop Pulse Width Modulation (PWM) Class D amplifiers are attractive for power critical applications including hearing aids due to their simple hardware and high power-efficiency. Nevertheless, a drawback of open-loop Class D amplifiers is their susceptibility to supply noise, quantified by power supply rejection ratio (PSRR) and power supply induced intermodulation distortion (PS-IMD). In this paper, PSRR and PS-IMD of a commonly-used carrier generation method are investigated and compared against other common carrier generation methods. The analyses are verified by means of HSPICE simulations. The analyses and comparisons provide designers useful insight to the design of power critical Class D amplifiers.

Perhaps most imperatively, design methods to minimize the IMD in Bang-bang CDAs are largely unknown, including the potential trade-offs with other parameters.Simply put, at this juncture, designers design Bang-bang CDAs largely based on intuition (and experience), and an analytical basis for their designs for the IMD is apparently lacking.