Sandia National Laboratories has been operating the Mykonos linear transformer driver (LTD) in a five-cavity configuration since 2014. The machine operates at 1MA output current, 500kV output voltage, with a 10-90% current rise time of 85ns, which enables small scale physics and engineering pulsed power experiments. Mykonos provides hands-on pulsed power experimental training for students and staff along-side senior Sandia scientists in an environment that is more accessible than the Z Facility. Over the years, we have fielded and accumulated a wide variety of optical, x-ray and electrical diagnostics and we are preparing to open this facility to outside users. Here, we are presenting the pulsed power and diagnostic capability of Mykonos as well as some recent experiments that have been performed on the facility. The goal of this publication is to attract researchers across the pulsed power and high energy density (HED) community to collaborate with Sandia on exciting, innovative science and to train the next generation of researchers for the National Nuclear Security Agency (NNSA) and the nation. As such, we have established a Mykonos Academic Access Program (MAAP) as part of ZNetUS to enable academic utilization of the Mykonos Pulsed Power Facility.

Deep level defects in wide bandgap semiconductors, whose response times are in the range of power converter switching times, can have a significant effect on converter efficiency. We use deep level transient spectroscopy (DLTS) to evaluate such defect levels in the n-drift layer of vertical gallium nitride (v-GaN) power diodes with VBD ∼ 1500 V. DLTS reveals three energy levels that are at ∼0.6 eV (highest density), ∼0.27 eV (lowest density), and ∼45 meV (a dopant level) from the conduction band. Dopant extraction from capacitance–voltage measurement tests (C–V) at multiple temperatures enables trap density evaluation, and the ∼0.6 eV trap has a density of 1.2 × 1015 cm−3. The 0.6 eV energy level and its density are similar to a defect that is known to cause current collapse in GaN based surface conducting devices (like high electron mobility transistors). Analysis of reverse bias currents over temperature in the v-GaN diodes indicates a predominant role of the same defect in determining reverse leakage current at high temperatures, reducing switching efficiency.

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. For electric vehicle drivetrains, this translates to higher efficiency and power density, resulting in more miles driven per charge. This move towards wide-bandgap power electronics is necessary to achieve the U.S. Department of Energy (DOE) power electronics density target of 100 kW/L. Vertical gallium nitride-based power devices are expected to exceed Si and even SiC-based systems with the promise of increased performance and power density. Compared to lateral GaN devices, a vertical topology promotes more efficient scaling towards high-power applications, where both high voltage and high current are necessary. This talk describes our team’s effort towards developing vertical GaN MOSFETs. The results of Sandia’s first-generation device demonstrator serve as a milestone in the path of producing devices rated for 1200-V and 100-A operation. The vertical GaN trench MOSFET is unique compared to Si- or SiC-alternatives in that the doped layers comprising the source and body regions are grown by epitaxy rather than formed by ion implantation. Challenges with selective-area doping in GaN add additional complexity to the design of a trench MOSFET. In addition, the lack of a high-quality native oxide in GaN means that the gate dielectric must be deposited rather than thermally grown. The devices produced at Sandia rely on atomic-layer-deposited thin films for the gate dielectric (primarily Al2O3 or SiO2). First-generation results demonstrate devices capable of 400 mA/mm drain current, 108 on/off ratio, and a positive threshold voltage near 8 V. More recently, devices capable of blocking 500 V in the off-state have been demonstrated. Device failure in the off-state results from high fields in the gate dielectric, which can be minimized by reducing the trench etch depth or by increasing the voltage rating of the drift region. However, further shielding of the gate dielectric to achieve substantially higher off-state voltages requires significant changes to the device architecture which are reliant on selective-area doping. In addition, device-killing defects either from the starting substrate, the epitaxy, or defects introduced during processing limit yield for large-area devices and present a substantial obstacle to scale devices for high-current operation. Hence, methods for reducing cell pitch and increasing packing density are highly valued. In this talk, we will discuss the path forward for achieving higher breakdown voltages and high-current operation using GaN-specific strategies to achieve better performing devices, as well as some of the challenges for vertical GaN development. This work provides a foundational platform for developing next-generation power electronics that employ wide bandgap, gallium nitride semiconductors. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

Understanding of semiconductor breakdown under high electric fields is an important aspect of materials’ properties, particularly for the design of power devices. For decades, a power-law has been used to describe the dependence of material-specific critical electrical field ( $${\mathcal{E}}_{\text{crit}}$$ E crit ) at which the material breaks down and bandgap ( E g ) . The relationship is often used to gauge tradeoffs of emerging materials whose properties haven’t yet been determined. Unfortunately, the reported dependencies of $${\mathcal{E}}_{\text{crit}}$$ E crit on E g cover a surprisingly wide range in the literature. Moreover, $${\mathcal{E}}_{\text{crit}}$$ E crit is a function of material doping. Further, discrepancies arise in $${\mathcal{E}}_{\text{crit}}$$ E crit values owing to differences between punch-through and non-punch-through device structures. We report a new normalization procedure that enables comparison of critical electric field values across materials, doping, and different device types. An extensive examination of numerous references reveals that the dependence $${\mathcal{E}}_{\text{crit}}$$ E crit ∝ E g 1.83 best fits the most reliable and newest data for both direct and indirect semiconductors. Graphical abstract

Etched-and-regrown GaN pn-diodes capable of high breakdown voltage (1610 V), low reverse current leakage (1 nA = 6 μA/cm 2 at 1250 V), excellent forward characteristics (ideality factor 1.6), and low specific on-resistance (1.1 mΩ.cm 2 ) were realized by mitigating plasma etch-related defects at the regrown interface. Epitaxial n-GaN layers grown by metal-organic chemical vapor deposition on free-standing GaN substrates were etched using inductively coupled plasma etching (ICP), and we demonstrate that a slow reactive ion etch (RIE) prior to p-GaN regrowth dramatically increases diode electrical performance compared to wet chemical surface treatments. Etched-and-regrown diodes without a junction termination extension (JTE) were characterized to compare diode performance using the post-ICP RIE method with prior studies of other post-ICP treatments. Then, etched-and-regrown diodes using the post-ICP RIE etch steps prior to regrowth were fabricated with a multi-step JTE to demonstrate kV-class operation.

This report describes the high-level accomplishments from the Plasma Science and Engineering Grand Challenge LDRD at Sandia National Laboratories. The Laboratory has a need to demonstrate predictive capabilities to model plasma phenomena in order to rapidly accelerate engineering development in several mission areas. The purpose of this Grand Challenge LDRD was to advance the fundamental models, methods, and algorithms along with supporting electrode science foundation to enable a revolutionary shift towards predictive plasma engineering design principles. This project integrated the SNL knowledge base in computer science, plasma physics, materials science, applied mathematics, and relevant application engineering to establish new cross-laboratory collaborations on these topics. As an initial exemplar, this project focused efforts on improving multi-scale modeling capabilities that are utilized to predict the electrical power delivery on large-scale pulsed power accelerators. Specifically, this LDRD was structured into three primary research thrusts that, when integrated, enable complex simulations of these devices: (1) the exploration of multi-scale models describing the desorption of contaminants from pulsed power electrodes, (2) the development of improved algorithms and code technologies to treat the multi-physics phenomena required to predict device performance, and (3) the creation of a rigorous verification and validation infrastructure to evaluate the codes and models across a range of challenge problems. These components were integrated into initial demonstrations of the largest simulations of multi-level vacuum power flow completed to-date, executed on the leading HPC computing machines available in the NNSA complex today. These preliminary studies indicate relevant pulsed power engineering design simulations can now be completed in (of order) several days, a significant improvement over pre-LDRD levels of performance.

We report on reliability testing of vertical GaN (v-GaN) devices under continuous switching conditions of 500, 750, and 1000 V. Using a modified double-pulse test circuit, we evaluate 1200 V-rated v-GaN PiN diodes fabricated by Avogy. Forward current-voltage characteristics do not change over the stress period. Under the reverse bias, the devices exhibit an initial rise in leakage current, followed by a slower rate of increase with further stress. The leakage recovers after a day's relaxation which suggests that trapping of carriers in deep states is responsible. Overall, we found the devices to be robust over the range of conditions tested.