Contact resistivity measurements of ohmic contacts to the nitrogen face (N-face) of n-type GaN substrates are determined using the Cox-Strack method. The contacts consist of sputtered Ti/W formed on two substrates with root-mean-square (rms) roughness of similar to 100 nm (rough) and similar to 5 nm (smooth) on the N-face. This is followed by the e-beam-evaporated Al and Al/Ni/Au onto the rough and smooth samples, respectively. The samples are tested as deposited and annealed at 300 degrees C, 400 degrees C, and 500 degrees C for 10 min. The contact resistivity for the asdeposited, smooth sample is 1.1 & times; 10(-4 )ohm-cm(2) , and that for the rough sample after a 500 degrees C anneal is 1.9 & times; 10(-5) ohm & centerdot;cm(2 ). For all other conditions, they are Schottky. The barrier height of the rough sample is 254 meV, assuming the thermionic field emission (TFE) model. This work highlights the utility and limitations of the Cox-Strack method for determining low contact resistivities in vertical semiconductor devices and for forming these contacts at low temperatures, thereby easing process constraints.

Wide-bandgap semiconductors have a significant advantage over conventional Si-based electronics by leveraging materials properties to achieve higher breakdown voltage, lower on-resistance, and high-frequency operation. For electric vehicle drivetrains, this translates to higher efficiency and power density, resulting in more miles driven per charge. This move towards wide-bandgap power electronics is necessary to achieve the U.S. Department of Energy (DOE) power electronics density target of 100 kW/L. Vertical gallium nitride-based power devices are expected to exceed Si and even SiC-based systems with the promise of increased performance and power density. Compared to lateral GaN devices, a vertical topology promotes more efficient scaling towards high-power applications, where both high voltage and high current are necessary. This talk describes our team’s effort towards developing vertical GaN MOSFETs. The results of Sandia’s first-generation device demonstrator serve as a milestone in the path of producing devices rated for 1200-V and 100-A operation. The vertical GaN trench MOSFET is unique compared to Si- or SiC-alternatives in that the doped layers comprising the source and body regions are grown by epitaxy rather than formed by ion implantation. Challenges with selective-area doping in GaN add additional complexity to the design of a trench MOSFET. In addition, the lack of a high-quality native oxide in GaN means that the gate dielectric must be deposited rather than thermally grown. The devices produced at Sandia rely on atomic-layer-deposited thin films for the gate dielectric (primarily Al2O3 or SiO2). First-generation results demonstrate devices capable of 400 mA/mm drain current, 108 on/off ratio, and a positive threshold voltage near 8 V. More recently, devices capable of blocking 500 V in the off-state have been demonstrated. Device failure in the off-state results from high fields in the gate dielectric, which can be minimized by reducing the trench etch depth or by increasing the voltage rating of the drift region. However, further shielding of the gate dielectric to achieve substantially higher off-state voltages requires significant changes to the device architecture which are reliant on selective-area doping. In addition, device-killing defects either from the starting substrate, the epitaxy, or defects introduced during processing limit yield for large-area devices and present a substantial obstacle to scale devices for high-current operation. Hence, methods for reducing cell pitch and increasing packing density are highly valued. In this talk, we will discuss the path forward for achieving higher breakdown voltages and high-current operation using GaN-specific strategies to achieve better performing devices, as well as some of the challenges for vertical GaN development. This work provides a foundational platform for developing next-generation power electronics that employ wide bandgap, gallium nitride semiconductors. This work was supported by the Electric Drivetrain Consortium managed by Susan Rogers of DOE’s Vehicle Technologies Office. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy or the United States Government. Figure 1

Impact ionization coefficients play a critical role in semiconductors. In addition to silicon, silicon carbide and gallium nitride are important semiconductors that are being seen more as mainstream semiconductor technologies. As a reflection of the maturity of these semiconductors, predictive modeling has become essential to device and circuit designers, and impact ionization coefficients play a key role here. Recently, several studies have measured impact ionization coefficients. We dedicated the first part of our study to comparing three experimental methods to estimate impact ionization coefficients in GaN, which are all based on photomultiplication but feature characteristic differences. The first method inserts an InGaN hole-injection layer, the accuracy of which is challenged by the dominance of ionization in InGaN, leading to possible overestimation of the coefficients. The second method utilizes the Franz–Keldysh effect for hole injection but not for electrons, where the mixed injection of induced carriers would require a margin of error. The third method uses complementary p–n and n–p structures that have been at the basis of this estimation in Si and SiC and leans on the assumption of a constant electric field, and any deviation would require a margin of error. In the second part of our study, we evaluated the models using recent experimental data from diodes demonstrating avalanche breakdown.

Vertical gallium nitride (GaN) p-n diodes have garnered significant interest for use in power electronics where high-voltage blocking and high-power efficiency are of concern. In this article, we detail the growth and fabrication methods used to develop a large area (1 mm 2 ) vertical GaN p-n diode capable of a 6.0-kV breakdown. We also demonstrate a large area diode with a forward pulsed current of 3.5 A, an 8.3- $\text{m}\boldsymbol \Omega \cdot {\text{cm}}^{2}$ differential specific ON-resistance, and a 5.3-kV reverse breakdown. In addition, we report on a smaller area diode (0.063 mm 2 ) that is capable of 6.4-kV breakdown with a differential specific ON-resistance of 10.2 $\text{m}\boldsymbol \Omega \cdot {\text{cm}}^{2}$ , when accounting for current spreading through the drift region at a 45° angle. Finally, the demonstration of avalanche breakdown is shown for a 0.063-mm 2 diode with a room temperature breakdown of 5.6 kV. These results were achieved via epitaxial growth of a 50- $ \mu \text{m}$ drift region with a very low carrier concentration of $< 1\times10$ 15 cm −3 and a carefully designed four-zone junction termination extension.

Understanding of semiconductor breakdown under high electric fields is an important aspect of materials’ properties, particularly for the design of power devices. For decades, a power-law has been used to describe the dependence of material-specific critical electrical field ( $${\mathcal{E}}_{\text{crit}}$$ E crit ) at which the material breaks down and bandgap ( E g ) . The relationship is often used to gauge tradeoffs of emerging materials whose properties haven’t yet been determined. Unfortunately, the reported dependencies of $${\mathcal{E}}_{\text{crit}}$$ E crit on E g cover a surprisingly wide range in the literature. Moreover, $${\mathcal{E}}_{\text{crit}}$$ E crit is a function of material doping. Further, discrepancies arise in $${\mathcal{E}}_{\text{crit}}$$ E crit values owing to differences between punch-through and non-punch-through device structures. We report a new normalization procedure that enables comparison of critical electric field values across materials, doping, and different device types. An extensive examination of numerous references reveals that the dependence $${\mathcal{E}}_{\text{crit}}$$ E crit ∝ E g 1.83 best fits the most reliable and newest data for both direct and indirect semiconductors. Graphical abstract

Power semiconductor devices encounter stressful switching conditions in power electronic circuits [1]. Therefore, avalanche capability in power devices is highly desired, and its study is extremely important for realizing robust devices. Fortunately, GaN P-N junction possess avalanche capability, making vertical GaN devices with intrinsic P-N junctions robust against breakdown [2]. Most recently, vertical GaN P-N diodes with avalanche breakdown voltage up to 6 kV were reported [3]. However, most of these studies were done under DC, and a very few have investigated the avalanche behavior under circuit-level stresses such as unclamped inductive switching (UIS) stress. We previously reported unform and robust avalanche in our in-house fabricated 1.3 kV vertical GaN-on-GaN P-N diodes [4]. In our present work we extend our study to report the observation and role of current filament (microplasma tube) formed during avalanche conditions using the 1.3 kV GaN-on-GaN vertical P-N diode under UIS stress. We infer that the robustness in avalanche increased due to the movements of current filaments relieving the thermal stress.

This work investigates both avalanche behavior and failure mechanism of 3 kV GaN-on-GaN vertical P-N diodes, that were fabricated and later tested under unclamped inductive switching (UIS) stress. The goal of this study is to use the particular avalanche characteristics and the failure mechanism to identify issues with the field termination and then provide feedback to improve the device design. DC breakdown is measured at the different temperatures to confirm the avalanche breakdown. Diode's avalanche robustness is measured on-wafer using a UIS test set-up which was integrated with a wafer chuck and CCD camera. Post failure analysis of the diode is done using SEM and optical microscopy to gain insight into the device failure physics.

This work provides the first demonstration of vertical GaN Junction Barrier Schottky (JBS) rectifiers fabricated by etch and regrowth of p-GaN. A reverse blocking voltage near 1500 V was achieved at ~ 1 mA reverse leakage, with a sub 1 V turn-on and a specific on-resistance of 10 mΩ-cm2. This result is compared to other reported JBS devices in the literature and our device demonstrates the lowest leakage slope at high reverse bias. A large initial leakage current is present near zero-bias which is attributed to a combination of inadequate etch-damage removal and passivation induced leakage current.

Bulk 14-nm FinFET technology was irradiated in a heavy-ion environment (42-MeV Si ions) to study the possibility of displacement damage (DD) in scaled technology devices, resulting in drive current degradation with increased cumulative fluence. These devices were also exposed to an electron beam, proton beam, and cobalt-60 source (gamma radiation) to further elucidate the physics of the device response. Annealing measurements show minimal to no "rebound" in the ON-state current back to its initial high value; however, the OFF-state current "rebound" was significant for gamma radiation environments. Low-temperature experiments of the heavy-ion-irradiated devices reveal increased defect concentration as the result for mobility degradation with increased fluence. Furthermore, the subthreshold slope (SS) temperature dependence uncovers a possible mechanism of increased defect bulk traps contributing to tunneling at low temperatures. Simulation work in Silvaco technology computer-aided design (TCAD) suggests that the increased OFF-state current is a total ionizing dose (TID) effect due to oxide traps in the shallow trench isolation (STI). The significant SS elongation and ON-state current degradation could only be produced when bulk traps in the channel were added. Heavy-ion irradiation on bulk 14-nm FinFETs was found to be a combination of TID and DD effects.

This work reports an on-wafer study of avalanche behavior and failure analysis of in-house fabricated 1.3 kV GaN-on-GaN P-N diodes. DC breakdown is measured at different temperatures to confirm avalanche behavior. Diode's avalanche ruggedness is measured directly on-wafer using a modified unclamped inductive switching (UIS) test set-up with an integrated thermal chuck and high-speed CCD for real-time imaging during the test. The avalanche ruggedness of the GaN P-N diode is evaluated and compared with a commercial SiC Schottky diode of similar voltage and current rating. Failure analysis is done using SEM and optical microscopy to gain insight into the diode's failure mechanism during avalanche operation.