Superconductor digital integrated circuits (ICs) require rapid evaluation of multiple copies to obtain statistical operational data. These data are used for assessing model-to-hardware correlation and facilitate iterative IC design development. The Integrated Cryogenic Electronics Testbed (ICE-T) is a cryogen-free test platform, which can test multiple chips simultaneously with similar convenience to a liquid-helium immersion probe and with cool down times of between 3.3 to 4.5 hours. We have developed a three-chip insert to increase the volume of chip testing and demonstrated simultaneous cooling of six chips with two such inserts. We report the test statistics collected from 27 chips across a single wafer. We have also used the ICE-T's convenient temperature control system to evaluate chips in the 3.5 - 6 K range. Such evaluation determines the robustness of circuit design and its tolerance to critical current fluctuations due to fabrication variation.

Improving the efficiency in digital data transport, originating from 4 K superconductor integrated circuits (ICs) to standard room-temperature (300 K) electronics, both in terms of speed and power consumption, is vitally important for nearly all applications of superconductor digital electronics. The required data link must include all necessary amplification and conditioning to convert digital data from single flux quantum (SFQ) logic to standard CMOS logic levels. Therefore, one must minimize the overall power consumption for the required total data throughout by taking into account all parts of the link: 1) data transmitters or output drivers with SFQ input, 2) additional amplifiers, 3) transmission lines, and 4) data receivers at room-temperature, such as the ones available on commercial field-programmable gate arrays (FPGAs). Here, we describe two variants of electrical data links, with and without cryogenic semiconductor amplifiers.

Efficiently amplifying the high-speed and low-voltage swing outputs of single flux quantum (SFQ) logic to levels that are suitable for interfacing with room temperature electronics has been a long-standing challenge in the field of superconducting electronics. In this work, we investigate the feasibility of using a lossy passive matching network at 4 K, with a pair of differential 100 low-noise amplifiers heatsunk to 18 K and 50 K stages, respectively. The amplifiers were implemented in a 120 nm SiGe BiCMOS technology. The amplification chain is dc coupled and the small-signal link gain was measured to be approximately 48 dB. The power consumption of each of the two amplification stages was 6.3 mW. The chain was measured at 21 K using a high-speed differential nonreturn-to-zero signal having amplitude commensurate with what one would expect from a superconducting circuit, and clean eye diagrams were observed for data rates as high as 30 Gb/s. The chain was also measured when driven from an SFQ/dc interface, with the first gain stage heatsunk to 9 K. In this configuration, clean eye diagrams were observed to 5 Gb/s, with the speed limitation being related to packaging parasitics.

As the digital data links for superconducting circuits advance and higher data throughput per channel becomes possible, timing margins shrink and data integrity becomes a major challenge. Particular interest for multichannel applications is establishing the high-quality data link to interface with subsequent electronics. In this paper, we focus on integration of an on-chip pseudorandom binary sequence (PRBS) generator into a superconducting analog-to-digital converter (ADC) design to facilitate link stability evaluation and automated interchannel synchronization. PRBS generator and the ADC use a common clock source. An on-chip deserializer/ demux, which includes the output drivers, is driven by a set of data sources depending on switch selections on-chip. The outputs are connected to a field-programmable gate array (FPGA) at room temperature, which hosts the developed interface circuitry for data reception, data integrity evaluation, and the synchronization mechanism. The integrated circuit (IC) that combines ADC and PRBS7 generator circuit was designed for the HYPRES 4.5 kA/ cm(2) four-layer standard fabrication process and features four deserialized outputs. A second similar IC was designed comprising an ADC frontend as well as a PRBS15 generator and was fabricated in the MIT-LL 10 kA/ cm(2) process. The implemented alignment engine that bonds the individual channels into a single data link was proven up to 10 Gbps while taking 1-2 mu s to complete the alignment. We built chip-to-FPGA data links, comprising the on-chip driver and room-temperature interface amplifier, up to 14 Gbps using FPGA serial-link GTY transceiver. Successful data transport from an ADC using multiple parallel data links to an FPGA upon completion of the channel bonding was demonstrated.

Future development of superconductor digital and mixed-signal ICs requires extensive testing with a large number of input/output (I/O) lines for applying independent bias controls, injecting test signals, and monitoring outputs of different subcircuits. There is a growing need for a standardized test apparatus for a variety of complex superconducting chips and multichip modules (MCMs). Such a test apparatus must support many I/O lines, be easy and cost-effective to operate, and support prolonged automated testing. Existing test apparatus include liquid He cryoprobes and cryocooled custom digital-RF systems, both of which have drawbacks. LiquidHe cryoprobes with universal wiring, such as 40 or 80 coaxial cables, are convenient to use. Cooled by immersion in a tank filled with liquid He, these cryoprobes allow rapid cool-down and warm-up. However, large consumption of liquid He, the cost of which has been steadily increasing worldwide, makes this solution rather expensive and wasteful. On the other hand, one can exploit the modular reconfigurability of HYPRES' digital-RF receiver product to create a testbed for different ICs. Such a system uses the smallest commercially available closed-cycle refrigerator (similar to 1.2 kW) and has negligible operating cost. However, reconfiguration takes time and expertise since these products are specially designed with customized chip package and wiring tominimize the thermal load on the cryocooler. These low-maintenance systems are ideal for prolonged operation of a single chip, which is invaluable for superconductor electronics system developers and end-users. The integrated cryoelectronics testbed (ICE-T) combines the advantages of the liquid He cryoprobe and the cryocooled digital-RF product. By using a more powerful, commercially available, electrically powered closed-cycle refrigerator (7 kW), ICE-T alleviates the thermal constraints on wiring while maintaining very low operating cost. By separating the electrical and thermal subsystems, it maintains modularity without sacrificing the universality of the cryoprobe. A set of universal and custom electrical modules can be independently built and inserted in ICE-T. Universal inserts with 40 and 80 coaxial cables accommodate all chips with standard I/O pads like the familiar liquid He cryoprobes. Custom inserts for different classes of chips and MCMs are designed and built according to user requirements and specifications. The utility of the ICE-T was successfully demonstrated by testing a benchmark superconducting digital circuit at low frequency and an analog-to-digital converter chip clocked above 20 GHz.

Research and development of cryogenic application-specific integrated circuits (ASICs), such as high-frequency (tens of GHz) semiconductor and superconductor mixedsignal circuits and large-scale (> 10,000 Josephson Junctions) superconductor digital circuits, have long been hindered by the absence of specialized cryogenic test apparatus. During their iterative development phase, most ASICs require many additional input-output lines for applying independent bias controls, injecting test signals, and monitoring outputs of different sub-circuits. We are developing a full suite of modular test apparatus based on cryocoolers that do not consume liquid helium, and support extensive electrical interfaces to standard and custom test equipment. Our design separates the cryogenics from electrical connections, allowing even inexperienced users to conduct testing by simply mounting their ASIC on a removable electrical insert. Thermal connections between the cold stages and the inserts are made with robust thermal links. ICE-T accommodates two independent electrical inserts at the same time. We have designed various inserts, such as universal ones with all 40 or 80 coaxial cables and those with customized wiring and temperature-controlled stages. ICE-T features fast thermal cycling for rapid testing, enables detailed testing over long periods (days to months, if necessary), and even supports automated testing of digital ICs with modular additions.

Interfacing superconducting rapid single flux quantum logic with room temperature electronics requires the development of low-power semiconductor circuitry capable of operating at tens of Gb/s while maintaining sufficient signal to noise to achieve acceptable bit-error-rates. Such data-links must operate with sufficiently low power consumption to permit tens to hundreds of parallel channels to coexist in a single cryostat. This requires a careful trade-off between the power and noise performance of the cryogenically cooled digital amplifiers. Previously demonstrated ultra low-power cryogenic-to-room temperature digital data links have been limited to data rates on the order of a few Gb/s. In this paper we demonstrate a temperature distributed amplifier chain optimized for 30 Gb/s data transmission and consuming just 140 microwatts at 4 K.

Integration of multiple synchronous identical superconductor analog-to-digital converters (ADCs) on a single chip or a multi-chip module is attractive for numerous applications, including Magnetic Resonance Imaging (MRI) systems. Several dual-ADC chips comprising two phase modulation-demodulation (PMD) ADCs with a common sampling clock, each connected to a digital decimation filter, have been designed. One variant with a single-junction quantizer with two-channel synchronizer and a decimation ratio of 256 has been installed in a modular cryocooled digital-RF receiver system (called ADR), operated with a common clock frequency of 20.48 GHz, and extensively tested with single and multiple input signals. Other variants have reduced decimation ratio for higher RF bands to digitize signals from higher-field MRI systems. Another variant of multi-input ADC integrated circuit chips have no on-chip filtering. We have designed and tested 2 (dual), 3 (tri), and 4 (quad) input versions of such a chip, where each ADC is followed by a deserializer circuit. A proof-of-concept multi-chip module (MCM) with 8 (octo) synchronous ADCs, consisting of four flipped dual-ADC chips on a carrier, has been designed to demonstrate scalability. 

We report on the experimental study of flip chip bonded niobium-based superconducting multichip module (MCM) using a nano-engineered cryogenic adhesive (nECA) for a cryogenic underfill that uses single-wall carbon nanotubes. Two MCMs, each having a 5 × 5 mm 2 chip flip chip bonded onto a 1 × 1 cm 2 carrier chip, were made with the nECA and pure cryogenic underfill for comparative analysis. The MCMs (1 × 2) were then mounted on a cryocooler and the thermal performances of the two modules were compared. The MCM bonded using nECA demonstrated a 58% decrease in temperature gradient between chip and carrier with respect to the pure cryogenic underfill. Additionally, we report the I - V characteristic of 20 unshunted Josephson junctions on the chip and the carrier as a function of carrier temperature and applied power for the MCM bonded using nECA. The MCM was thermal cycled between room temperature and 4.2 K, and the I - V measurements were repeated at 4.2 K. The experimental study demonstrated that single-wall carbon nanotubes integrated underfill enhanced the thermal performance without affecting the electrical performance. This finding presents a novel nano-engineered packaging material and approach for increased functional modularity for superconducting MCMs.

Superconducting single flux quantum (SFQ) circuits can process information at extremely high speeds, in the range of hundreds of GHz. SFQ circuits are based on Josephson junction cells for switching logic and ballistic transmission for transferring SFQ pulses. Multi-chip modules (MCMs) are often used to implement larger complex designs, which cannot be fit onto a single chip. We have optimized the design of wideband interconnects for transferring signals and SFQ pulses between chips in flip-chip MCMs and evaluated the importance of several design parameters such as the geometry of bump pads on chips, length of passive microstrip lines (MSLs) and number of corners in MSLs as well as flux trapping and fabrication effects on the operating margins of the MCMs. Several test circuits have been designed to evaluate the above mentioned features and fabricated in the framework of a 4.5 kA cm(-2) HYPRES process. The MCM bumps for electrical connections have been deposited using a wafer-level electroplating process. We have found that, at the optimized configuration, the maximum operating frequency of the MCM test circuit, a ring oscillator with chip-to-chip connections, approaches 100 GHz and is not noticeably affected by the presence of MCM interconnects, decreasing by only about 3% with respect to the same circuit with no inter-chip connections.

We report the development of a nano-engineered cryogenic adhesive (nECA) consisting of an epoxy impregnated with single walled carbon nanotubes (SWNT) for bonding niobium-based superconductor multi-chip modules (MCMs). The nECA offers 300%-900% enhancement in thermal conduction over the base adhesive while maintaining high electrical resistivity. Additionally, we report the thermal modeling results for a niobium-based superconducting single chip module with the incorporation of pure epoxy and nECA. When the heat flow is exclusively through the In/Sn bumps the thermal model predicts >; 100 mK temperature difference between the flipped chip with active circuitry and the passive carrier substrate, which might degrade the chip's performance and the operating margins. With the use of 0.1 wt% SWNT loaded epoxy as the underfill, we report reduction of temperature differences to a more acceptable level of ~ 19 mK. These results are expanded to foreseeable MCM package designs to highlight the merit of nECA as an underfill material for superconducting electronic packages.

We report the experimental study of the thermal resistance of a flip chip bonded superconducting multichip module (MCM) in a liquid cryogen free environment. A 5×5 mm2 indium-tin bumped superconducting chip was flip chip bonded on a 1×1 cm2 superconducting carrier chip. A non-conductive adhesive was used as an underfill to enhance the robustness of the package. We designed a test bed where the LSCE module was mounted onto the cold head of a Gifford McMahon (GM) cryocooler. The module was conductively cooled down to 4 K and the thermal resistance between the chip and the carrier chip was analyzed. The experimental results showed that for the power dissipation (2 – 5 mW), which is typical for low temperature superconducting electronic LSCE devices, the thermal resistance was 20.1 +/− 1.9 K/W. Thermal model of the current LSCE package was investigated using COMSOL multi-physics. Theoretical estimates showed that for the current package setup the expected thermal resistance of the bump path to be 6.2 K/W. The discrepancy between the model and experimental analysis has been explained due to the presence of voids and inadequate bump contact area. To our knowledge, this is the first such experimental investigation of the thermal performance of adhesive bonded LSCE package on a cryocooler. This experimental analysis is of paramount importance for future trends in single chip and multichip module packaging of LSCE devices.

A software radio receiver that can be programmed to operate in multiple wide frequency bands is required for many communication and intelligence applications. We have designed a variety of multi-band receivers, comprising a set of band-specific analog-to-digital converters (ADCs) for direct digitization of RF bands and a digital switch matrix for band selection, in two flavors: as a single superconductor integrated circuit chip and also as a multi-chip module. In addition to the ADCs and the switch, these include a 1:16 deserializer and output drivers to facilitate transport of the digitized RF data to room temperature electronics for further processing and analysis. In the single IC flavor, up to four bandpass delta-sigma ADCs minimizing quantization noise in their respective bands were integrated on the same chip and operated at clock rates up to 20 GHz. In the multi-chip module (MCM) implementation, a 1-cm × 1-cm universal active carrier was designed to accommodate any two 2.5-mm × 2.5-mm flipped chips, each containing a single ADC front-end. This standardized approach facilitates customization of two-band ADCs by selecting from a growing library of ADC front-ends, which currently cover bands ranging from HF (0-30 MHz) to Ka-band (20-21 GHz). These Multi-band MCMs and single chip ADC's were fabricated, assembled and tested.

Superconductor digital receiver systems of increasing functionality, modularity and user-friendliness have been developed. The modular design methodology ensures that within its input-output and heat load capacity, the system can be reconfigured to perform a different function by changing the chip module and by reprogramming FPGA-based digital signal processors. One of the systems (ADR-004), originally equipped with a 10 × 10 mm2 channelizing receiver chip for signals intelligence application, was reconfigured with a 5 × 5 mm2 1.1-GHz bandpass ADC chip to perform world's first multi-net Link-16 demonstration at a U.S. Navy facility. Substantial improvements in system integration have been obtained in each successive generation of digital-RF receiver systems. The latest (third) generation system (ADR-005), hosting a 5 × 5 mm2 7.5-GHz bandpass ADC chip and an FPGA channelizer, successfully repeated the over-the-air SATCOM demonstration performed previously using a 1-cm2 single-chip bandpass digital receiver with an on-chip superconductor channelizer. This system ran error-free for over 12 hours with and without a low-noise amplifier. To our knowledge, this is the first time an X-band SATCOM receiver has been operated without analog amplification and down-conversion in a military application.

In the current research we have developed a thermally enhanced and electrically non-conductive nano-integrated adhesive for ultra-low temperature (4K) cryogenic microelectronic packaging. Ultra-low temperature niobium based (4K) superconductor microelectronics offer the unique combination of ultrafast switching speeds (up to 100GHz), high sensitivity and low power consumption. The commercialization of these cryogenic microelectronic devices in a complex multichip module architecture where the integration of heterogeneous material and increased power density is generating a need to develop new materials and techniques to enhance the thermal and electrical performance of these ultra-low temperature superconducting microelectronic packages. In the current research, authors have investigated the thermal behavior of single-walled carbon nanotube integrated adhesive for the packaging of ultra-low-temperature (4K) electronics. Test vehicles loaded with varying concentrations of purified single-walled carbon nanotube (SWNT) integrated adhesive were characterized at 4K. The nano-integrated adhesive showed increasingly higher thermal conductivity than the pure adhesive with higher loading concentration. The thermal analysis of the nano-integrated adhesive suggests that single-walled carbon nanotube filled adhesive can play a profound role as an underfill and die attach in cryo-packaging for ultra-low temperature high density multi-chip modules (MCM).

HYPRES is developing a class of digital receivers featuring direct digitization at radio frequency. The complete system, consisting of a cryopackaged Nb superconductor all-digital receiver (ADR) chip followed by room-temperature interface electronics and a field-programmable gate array (FPGA) based post-processing module, has been developed. Depending on the targeted application the ADR chip comprised either a low-pass delta with phase modulation-demodulation architecture or X-band band-pass sigma-delta modulators together with digital in-phase and quadrature mixer and a pair of digital decimation filters. The chips were fabricated using a 4.5-kA/cm 2 HYPRES process and were cryopackaged using a commercial-off-the-shelf cryocooler. Recently, with significant improvements in chip cryopackage, room-temperature electronics and FPGA programming we were able to achieve stable operation of a low-pass ADR at 28.16 GHz and X-band ADR at 30.72 GHz clock frequencies. Experimental results are presented and discussed.

A custom-designed laboratory prototype of a four-stage Stirling-type pulse tube cryocooler was recently developed by Lockheed Martin for niobium integrated circuits (ICs) operating close to 4 K. Basic system performance has been verified by integration with a Nb IC test chip, with cells that include a high-speed rapid single flux quantum (RSFQ) binary counter. For 650 W total compressor power, extended stable operation of the counter at T=4.5 K was demonstrated with a clock frequency up to 46 GHz, with 25 mW of excess cooling capacity on the coldest stage. The thermodynamic, electromagnetic, and mechanical performance are promising for the development of an improved compact cryocooler for practical superconducting electronic applications in fields such as wireless communications.