We experimentally demonstrate a visible light communication (VLC) system based on a single commercially available RGB-type LED. High spectrally efficient carrier-less amplitude and phase (CAP) modulation and orthogonal frequency-division multiplexing (OFDM) are adopted in the intensity-modulation and direct-detection VLC system of limited bandwidth. In order to achieve higher capacity of the uneven-frequency-response LED-based VLC system, OFDM signals are combined with the bit-and power-loading techniques, and CAP signals of various modulation are pre-emphasized to modulate one of the RGB chips. To reach the BER of less than 10(-3), CAP and OFDM signals demonstrate the maximum data rates of 1.32 and 1.08 Gb/s, respectively, employing the blue chip. In addition to spectrally efficient formats, the wavelength-division-multiplexing (WDM) scheme is applied to further increase the capacity. After individually optimizing RGB chips, the maximum aggregate data rates of CAP and OFDM are 3.22 and 2.93 Gb/s, respectively, in our RGB-LED-based WDM VLC system. Hence, compared with OFDM, the CAP scheme shows competitive performance and provides an alternative spectrally efficient modulation for next generation optical wireless networks.

A new continuous semi-empiric compact model for the current transfer characteristics of surrounding gate undoped polycrystalline silicon (Poly-Si) nanowire (NW) MOSFETs is proposed. The model consists of a single equation based on the Lambert function, which contains only four parameters and is continuously valid and fully differentiable throughout weak and strong conduction regimes of operation. The model is tested on measured transfer characteristics of experimental devices. The extracted model parameters are used to generate transfer characteristics playbacks that are then compared to the measured data to validate the proposed model's adequacy for these devices. (C) 2011 Elsevier Ltd. All rights reserved.

A new double integration-based method to extract model parameters is applied to experimental polysilicon nanowire MOSFETs. The threshold voltage and Subthreshold Slope factor are extracted from noisy measured current–voltage characteristics. It is shown that the present method offers advantages over previous extraction procedures regarding data noise reduction. In addition, the normalized mutual integral difference operator method is scrutinized and an improvement of the method is presented.

In this work, the degradation mechanism of N-channel poly-silicon thin-film transistor (poly-Si TFT) has been investigated under dynamic voltage stress at room temperature. The ON-current of TFT is degraded to as low as 0.3 times of the initial value after 1000s stress. On the other hand, both the sub-threshold swing and threshold voltage kept well during the AC stress. The current crowding effect was rapidly increased with increasing of stress duration. However, comparing the initial and degraded characteristics at rising temperature, namely, 150°C, the ON-current of TFT only decrease to 75% of the initial value after 1000s AC stress. It depicts that creation of effective trap density in tail-states of poly-Si film is responsible for the electrical degradation of poly-Si TFT. At high temperature, electron has enough energy to pass the energy barrier created by ac stress and the degradation is less obvious.

SID Symposium Digest of Technical PapersVolume 36, Issue 1 p. 1152-1555 27.2: Characterizations of Flash Memory on Glass Using LTPS TFT with an Ultra-Low-Roughness Poly-Si/SiO2 Interface Hung-Tse Chen, Hung-Tse Chen Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorPo-Hao Tsai, Po-Hao Tsai Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorYu-Cheng Chen, Yu-Cheng Chen Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorChi-Lin Chen, Chi-Lin Chen Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorJia-Xing Lin, Jia-Xing Lin Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorJason C. Chang, Jason C. Chang Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorC. W. Chen, C. W. Chen Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan, R. O. C.Search for more papers by this authorH. Y. Lu, H. Y. Lu Department of Photonics & Display Institute, National Chiao Tung University, Hsin-Chu, Taiwan, R. O. C.Search for more papers by this authorH. H. Wu, H. H. Wu Department of Photonics & Display Institute, National Chiao Tung University, Hsin-Chu, Taiwan, R. O. C.Search for more papers by this authorP. T. Liu, P. T. Liu Department of Photonics & Display Institute, National Chiao Tung University, Hsin-Chu, Taiwan, R. O. C.Search for more papers by this authorT. C. Chang, T. C. Chang Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, R. O. C.Search for more papers by this author Hung-Tse Chen, Hung-Tse Chen Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorPo-Hao Tsai, Po-Hao Tsai Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorYu-Cheng Chen, Yu-Cheng Chen Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorChi-Lin Chen, Chi-Lin Chen Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorJia-Xing Lin, Jia-Xing Lin Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorJason C. Chang, Jason C. Chang Electronics Research and Service Organization, Industrial Technology Research Institute, Hsinchu, Taiwan 310, R.O.C.Search for more papers by this authorC. W. Chen, C. W. Chen Institute of Electronics, National Chiao Tung University, Hsin-Chu, Taiwan, R. O. C.Search for more papers by this authorH. Y. Lu, H. Y. Lu Department of Photonics & Display Institute, National Chiao Tung University, Hsin-Chu, Taiwan, R. O. C.Search for more papers by this authorH. H. Wu, H. H. Wu Department of Photonics & Display Institute, National Chiao Tung University, Hsin-Chu, Taiwan, R. O. C.Search for more papers by this authorP. T. Liu, P. T. Liu Department of Photonics & Display Institute, National Chiao Tung University, Hsin-Chu, Taiwan, R. O. C.Search for more papers by this authorT. C. Chang, T. C. Chang Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan, R. O. C.Search for more papers by this author First published: 05 July 2012 https://doi.org/10.1889/1.2036205Citations: 5AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onEmailFacebookTwitterLinkedInRedditWechat Abstract In this paper, flash memories using low temperature poly-Si thin- film transistors (LTPS-TFTs) with oxide-nitride-oxide (ONO) stack structure on glass was studied and fabricated. The surface roughness Rms of poly-Si implemented in this work is less than 20Å. For 10 ms program/erase (P/E) pulse time, the threshold voltage window of memory is 1.5V and it maintains a wide threshold voltage window after 104 P/E cycles. References H. Kimura, et al, SID Symposium Digest 32, PP., 268, (2001). 10.1889/1.1831847 Google Scholar M. Senda, et al, SID Symposium Digest 33, PP., 790, (2002). 10.1889/1.1830901 CASGoogle Scholar H. Tokioka et. al., SID Symposium Digest 32, PP., 280, (2001). 10.1889/1.1831851 Google Scholar N. -I. Lee, J. -W. Lee, H. -S. Kim and C. -H. Han, IEEE Electron Device Letters, 20 (1), 15 (1999). 10.1109/55.737559 CASWeb of Science®Google Scholar N. D. Young, G. Harkin, R. M. Bunn, D. J. McCulloch, and I. D. French, IEEE Trans. on Electron Devices, 43 (11), 1930 (1996). 10.1109/16.543029 CASWeb of Science®Google Scholar Y. -C. Chen, et al, SID Symposium Digest 34, PP., 216, (2003). 10.1889/1.1832241 CASGoogle Scholar K.-H. Wu, T.-S. Chen, S.-C. Hsu, and C.-H. Kao, Journal of C.C.I.T., 32(1), 2003. Google Scholar Citing Literature Volume36, Issue1May 2005Pages 1152-1555 ReferencesRelatedInformation

We systematically investigated the effect of post-deposition-annealing (PDA) on the electrical characteristics of Ge MOS capacitors with hafnium-oxynitride gate dielectric. The higher PDA temperature and longer PDA time was found to obtain the lower equivalent oxide thickness (EOT) of HfO"xN"y/Ge gate stack, however, with a larger hysteresis width. A lower EOT of 19.5 A with a low leakage current of 1.8x10^-^5A/cm^2 at V"G=-1V was achieved after 600 ^oC annealing for 5 min. The improved capacitor properties after the PDA may be closely related to the different compositions and thicknesses of the resultant interfacial layers.

The device degradation caused by the hot-electron-induced electron trapping in the ultrathin (equivalent oxide thickness = 1.6 nm) nitrided gate oxide for the 0.13 mu m n-metal oxide semiconductor field effect transistors (n-MOSFETs) has been investigated. We have found that the nitrogen, incorporated in the gate dielectrics by a variety of popular techniques including Si3N4/SiO2 (N/O) stack, NO annealing, and plasma nitridation, results in enhanced hot-electron-induced device degradations as compared to the conventional gate oxide counterpart. The enhanced hot-electron degradations are attributed to the electron trap generation in the ultrathin gate dielectric rather than the interface state generation as a result of nitrogen incorporation. (c) 2005 The Electrochemical Society.

In recent years, manufacturing processes have become more and more complex, and meeting high-yield target expectations and quickly identifying root-cause machinesets, the most likely sources of defective products, also become essential issues. In this paper, we first define the root-cause machineset identification problem of analyzing correlations between combinations of machines and the defective products. We then propose the Root-cause Machine Identifier (RMI) method using the technique of association rule mining to solve the problem efficiently and effectively. The experimental results of real datasets show that the actual root-cause machinesets are almost ranked in the top 10 by the proposed RMI method.

In this work the dielectric properties of plasma enhanced chemical vapor deposited (PECVD) amorphous SiOC (α-SiOC) films with various concentrations of oxygen are investigated for the barrier dielectric application. Experimental results show after fluorine (F) ion implanted into α-SiOC film, the leakage current in carbide film is increased due to the generation of trap centers. Afterwards, the traps can be effectively repaired after thermal annealing, leading to the decrease of leakage current further. From the extraction of the current–voltage (J–E) characteristics, the conducting mechanism of the leakage current obeys the Poole–Frenkel type behavior for intrinsic, F-implanted and thermally annealed samples. Also, the barrier height of the F-implanted and thermally annealed samples are extracted and exhibits a higher value than that of the intrinsic sample.

We have generated porous polybenzoxazine (PBZZ) materials by using a B-a type PBZZ as the matrix and various molecular weights of poly(ε-caprolactone) (pa-PCL) as the labile constituent. The slight degree of hydrogen bonding that exists between the two polymers results in micro-phase separation without an excess degree of aggregation occurring. The porous structures form after hydrolysis of the PCL domains; we characterized them using a variety of techniques, including FT-IR spectroscopy, DSC, TGA, FE-SEM, and DEA. At 298K and 105Hz, we obtained a thin, transparent, and nanoporous film that has a very low dielectric constant (1.95).

With the replacement of silicon nitride in an oxide/nitride/oxide (ONO) gate-stacked structure, trap-rich high-density plasma chemical vapor deposited (HDPCVD) SiNx shows a more significant threshold-voltage shift (memory window) than that of conventional low pressure (LP)CVD Si3N4. Also, low-temperature (2000degreesC) deposited HDPCVD silicon nitride shows a good retention characteristic, the same as high-temperature (780degreesC) LPCVD Si3N4. With the optimization of thickness in the gate-stacked ONO structure, low-voltage and reliable operation, lower than 5 V, is realizable. (C) 2004 The Electrochemical Society.

The leakage behavior of the quasi-superlattice structure has been characterized by current–voltage measurements at room temperature and 50 K. A resonant tunnelinglike leakage characteristic is observed at low temperature. The resonant tunneling occurs at around 2, 5.2, and 7 V under a gate voltage swept from 0 to 10 V. A concise physical model is proposed to characterize the leakage mechanism of tunneling for the quasi-lattice structure and suggests that the considerations of the operating voltage for the two-bit per cell nonvolatile-memory device need to be taken into account.

Pattern profile distortion of nanoporous organosilicates has been investigated after pattern transfer processes. After photoresist stripping with O-2-plasma ashing, many organic function groups are destroyed and sequentially transformed into siloxanol groups (Si-OH) in the nanoporous organosilicates. The interaction between siloxanol groups and the gelation reaction occurred in the internal porous organosilicates predominate stress evolution, leading to the deformation of patterned porous organosilicate films. This physical mechanism responsible for pattern distortion and stress evolution can be consistently confirmed through the residual stress vs. temperature measurement and Fourier transform infrared spectroscopy. (C) 2003 The Electrochemical Society.

2 ! is demonstrated. Under a suitable operating voltage, two apparent states of charge storage can be distinguished. The memory effects are due to the multilevel charge storage within the quasi- superlattice. The multilevel charge storage provides a feasible design for the 2-bit-per-cell nonvolatile memory devices. Also, the leakage behavior of the quasi-superlattice structure has also been characterized by current-voltage measurements at room tem- perature and low temperatures. The resonant tunneling-like leakage characteristic is observed at low temperatures. A concise physical model is proposed to characterize the leakage mechanism of tunneling for the quasi-superlattice structure, and this suggests that consideration of the operating voltage for the 2-bit-per-cell nonvolatile memory device needs to be taken into account.

In recent years, the procedure of manufacturing has become more and more complex. In order to meet high expectation on quality target, quick identification of root cause that makes defects is an essential issue. In this paper, we will refer to a typical algorithm of mining association rules and propose a novel interestingness measurement to provide an effective and accurate solution. First, the manufacturing defect detection problem of analyzing the correlation between combinations of machines and the result of defect is defined. Then, we propose an integrated processing procedure RMI (Root cause Machine Identifier) to discover the root cause in this problem. Finally, the results of experiments show the accuracy and efficiency of RMI are both well with real manufacturing cases.

With huge amount of semiconductor engineering data stored in database and versatile analytical charting and reporting in production and development, the CIM/MES/EDA systems in the most semiconductor manufacturing companies help users to analyze the collected data in order to achieve the goal of yield enhancement. However, the procedures of semiconductor manufacturing are sophisticated and the collected data among these procedures are thus becoming high-dimensional and huge. Currently, some statistical methods, such like K-W test, covariance analysis, regression analysis, etc., have been used to analyze the information summarized from EDA system, and thus generate too many indexes that can not be easily judged and assimilated by engineers. Besides, too many false alarms may be raised and lots of time is required to check the factuality among them. In order to deal with the large amount and high-dimensional data, the data mining technologies are thus used to solve such problems. In this paper, we would like to propose a data mining solution and describe the experiences applying such solutions for discovering the root causes of low-yield situations in a worldwide semiconductor manufacturing company. Also, the situation of applying such mining solution for manufacturing defects detection in semiconductor manufacturing domain will be reviewed. Finally, the architecture of a reasonable, reliable and flexible data mining system will be briefly described.

A nonvolatile memory device embedded with Ge nanocrystal dots is fabricated by the thermal oxidation of Si0.8Ge0.2 combined with a rapid thermal annealing at 950degreesC in N-2 gas. The tunnel oxide in the nonvolatile memory is controlled to be 4.5 nm thick and embedded with 5.5 nm Ge nanocrystals. A low operating voltage, 5 V, is implemented and a significant threshold-voltage shift, 0.42 V, is observed. When the electrons are trapped in the Ge nanocrystals, the effect of Coulomb blockade prevents the injection and storage of more electrons and decreases the leakage current. Also, the retention characteristics are tested to be robust. (C) 2003 The Electrochemical Society.

The effect of oxygen plasma treatment on methylsilsesquiazane (MSZ) dielectric was investigated for chemical mechanical planarization (CMP) process. Oxygen plasma treatment was implemented before CMP. Experimental results have shown that the polishing rate of MSZ film with O-2 plasma pretreatment is increased as much as two order of magnitude more than that of MSZ without O-2 plasma pretreatment. Moreover, the electrical properties of post-CMP MSZ are close to those of an as-cured MSZ. These results indicate that the modified surfaces resulting from O-2 plasma treatment increase the polishing rate of MSZ. After polishing, the MSZ film still maintains a low-k quality. (C) 2004 The Electrochemical Society.

Effects of oxygen plasma ashing on barrier dielectric SiCN films have been studied for various ashing conditions. According to X-ray photoelectron spectra analyses, Si-O-2 bonds appear at the surface of SiCN film after O-2 plasma ashing. The formation of the oxidized layer, SiOxCN, at the surface of the SiCN film effectively reduces the leakage current as a consequence. The leakage conduction of the SiCN films has been investigated to be Schottky emission at the fields between 0.4 and 1.2 MV/cm. Also, the increase of Schottky barrier height between SiCN and the metal is calculated to be 42 meV after O-2 plasma ashing. (C) 2004 The Electrochemical Society.