The RF front-end circuits for 433 MHz ASK receiver are proposed in this paper.The design methodology of the low noise amplifier and down-mixer is presented in detail from the aspects of noise,matching,voltage gain and linearity,with the parasitic effects of the package and ESD protection circuit being considered.Fabricated in 0.18 μm CMOS process,the RF front-end circuit totally consumes 10.09 mA from 1.8 V power supply.The major measurement results are described as follows: the low noise amplifier achieves 1.35 dB NF,17.43 dB gain and-8.90 dBm input-referred P1dB(at 50 Ω input impedance);the down-mixer features 7.57 dB NF,10.35 dB gain and-4.83 dBm input-referred P1dB(at 100 Ω input impedance).

A low phase noise fractional-N frequency synthesizer for CMOS UHF RFID reader is introduced in this paper. The phase noise requirements are summarized for the EPC global C1G2 and ETSI multi-protocol operation. A low drop-output regulator is presented to improve the phase noise performance of the VCO. Based on the error-feedback delta-sigma modulator,a coefficient reconfiguring technology has been introduced to improve the phase noise performance at intermediate frequency band. The proposed circuit is implemented with 0.18 μm RF CMOS process. The fractional-N frequency synthesizer achieves a phase noise of-108 dBc/Hz and-129.8 dBc/Hz at 200 kHz and 1 MHz offset from the carrier respectively. The whole chip draws 9.6 mA from the multiple power supply configuration.

A low phase noise PLL for 433 MHz ASK receiver was fabricated in 0.18 μm CMOS RF process.In this circuit,power supply configuration and layout were optimized to reduce noise coupling.LC filters,LDO regulator and digitally controlled switched capacitor array were implemented to increase phase noise performance of the VCO.Nonlinearity of phase/frequency detector and charge-pump was discussed for optimization and improvement of linearity.Measurement results showed that the PLL achieved a phase noise of-96.47 dBc/Hz and-126.96 dBc/Hz at 100 kHz and 1 MHz offset from the center frequency of 433 MHz,respectively,while drawing 7 mA of power from a 3.3 V supply.

A novel single-chip 860-960MHz band UHF RFID reader transceiver IC is fabricated in 0.18μm CMOS technology. The transceiver consists of a compact high-linearity low-noise-figure RF front-end, a programmable analog baseband for Rx path; and an image reject filter, a PGA, a switchable up-conversion modulator and a driver amplifier for Tx path. The 3-bit 3rd-order DSM fractional-N frequency synthesizer with optimized all-band phase noise performance is integrated to implement Rx/Tx frequency translation. The transceiver IC has a die area of 4mm×4mm. It achieves IIP3 of 13dBm, sensitivity of -75dBm in listen-before-talk (LBT) mode and -66dBm in normal mode in the presence of -4.4dBm self-jammer for the backscatter modulation while drawing 112mA from 3.3V power supply.

Several key issues including system noise figure, input linearity, LO phase noise performance and transceiver setting-up time are recapitulated in this paper for the design of single-chip UHF RFID reader. The reader Rx noise figure is different between LBT and normal mode. The input linearity is decided by the maximum interferer due to Tx-to-Rx leakage. Phase noise requirements are to meet with Tx transmission spectrum mask, and withhold adjacent interferer and in-band self-jammer. The transceiver setting-up time is determined by the larger value between frequency synthesizer switching time and DC-offset removal time. A low-power low-cost single-chip 0.18μm CMOS UHF RFID reader transceiver is verified based on the foregoing analyses.

In this paper, a 3.18~4.258GHz wideband and low phase noise LC VCO is proposed. Three binary-weighted switching capacitors are exploited to expand the bandwidth; On-chip LDO is utilized to suppress noise from power supply. Symmetrical noise filtering technique is used to suppress thermal noise from tail current and parasitic resistors of bonding wires. The circuit is implemented with 0.13μm RF CMOS process. The frequency tuning range is from 3.18GHz to 4.258GHz and phase noise is -120dBc/Hz at IMHz offset from 4.258GHz carrier. The Figure of Merit (FOM) is -181dB/Hz and maximum power consumption is 12.5mW.

A low phase noise VCO(voltage controlled oscillator)for single chip UHF RFID Reader is proposed.The regulator and filtering technology are adopted in order to suppress the noise from VDD and shot the second harmonic of current source for phase noise reduction in 1/f3 region.Meanwhile,proper L with a relative better Q value is chosen to improve phase noise in 1/f2 region.Low noise bandgap is also added in the propose VCO.The VCO is implemented using UMC0.18 μm MM/RF CMOS technology.Compared with the traditional VCO,simulation result shows the phase noise reduction is around 5 dB in all frequency regions.The center frequency of proposed VCO is 1.8 GHz with the tuning rage of 11% while the power consumption is 7.2 mA at 3.3 V.The VCO has phase noise of-127 dBc/Hz@1 MHz.

A transmitter front-end circuit applied in the portable UHF RFID reader is designed and fabricated in 0.18 μm CMOS process. The designed active I/Q up-mixer can realize all three modulation schemes specified in EPC Global Class-1Gen-2 protocol by switching the input signals of Q branch. With the realization of seven-class digitally adjustable conversion gain,the driver amplifier can effectively pre-amplify the output signals of up-mixer. Measured at 1.8 V power supply,the major performance parameters of the transmitter front-end circuit are described as follows:the up-mixer achieves-14.9 dB Vrmsinput-referred P1 dB,3.18 dB conversion gain and 13.20 dB NF,and the DA features 3.5 dBm output-referred P1 dB at 50 Ω,7.90～16.30 dB conversion gain variation,and 3.10～5.00 dB NF range.

A low phase noise LC voltage controlled oscillator for UHF radio frequency identification reader is presented in this paper. Symmetrical LC resonators and a low-dropout-regulator are used to suppress the noise from tail current and power supply, respectively. 3-bit switched-capacitor array for coarse tuning followed by MOS varactors for fine tuning to ensure a Low voltage controlled oscillator gain (<48 MHz/V). The circuit is implemented in IBM 0.18 mum CMOS process, and the measured phase noise is -136.25 dBc/Hz at 1 MHz offset from the carrier while drawing 4.5 mA from a 3.3 V supply.

This paper describes a 900MHz CMOS transmitter front-end for mobile UHF RFID reader including an I/Q up-mixer for frequency translation from IF to RF and a driver amplifier for signal pre-amplification. The proposed up-mixer can realize all the three modulation schemes specified in EPC Global C1G2 protocol. The driver amplifier can offer a seven-class adjustable conversion gain through a 3-bit gate bias control. Fabricated in IBM 0.18µm CMOS process, the transmitter front-end consumes a minimum current of 14mA from a 1. 8V power supply. The experimental results show that the up-mixer achieves -4. 9dBVrms IIP3, 3. 18dB conversion gain and 13.20dB NF, and the DA features 13. 5dBm OIP3 at 50O, 7. 90-16. 30dB conversion gain variation and 3.10-5.00dB NF range.