Carbon capture, utilization and storage (CCUS) technologies play an essential role in achieving Net Zero Emissions targets. Considering the lack of timely reviews on the recent advancements in promising CCUS technologies, it is crucial to provide a prompt review of the CCUS advances to understand the current research gaps pertained to its industrial application. To that end, this review first summarized the developmental history of CCUS technologies and the current large-scale demonstrations. Then, based on a visually bibliometric analysis, the carbon capture remains a hotspot in the CCUS development. Noting that the materials applied in the carbon capture process determines its performance. As a result, the state-of-the-art carbon capture materials and emerging capture technologies were comprehensively summarized and discussed. Gaps between state-of-art carbon capture process and its ideal counterpart are analyzed, and insights into the research needs such as material design, process optimization, environmental impact, and technical and economic assessments are provided.

In this paper, we propose a dual manipulation on wave-front in the X band based on a reconfigurable water-based metasurface. We design and test a metasurface integrated with a saline-water substrate and PIN diodes. We showed that the wave-front reflected by the metasurface can be modulated by both the degree of salinity and the diode pattern. With these two manipulating methods, the metasurface can not only control the amplitude of the scattered beams but also the beam deflection angles, which promises a more flexible and economical way to manipulate the wave-front. We provide two diode patterns to illustrate the performance. The experimental results agree well with our simulations, further verifying our designs. Superior than the conventional reconfigurable metasurfaces, the proposed metasurface combines both water salinity and diodes, which offers more possibilities in electromagnetic (EM) wave tailoring, as well as potential applications in sensing and detection.

在智能卡的设计中,集成电路器件特征尺寸变得越来越小.目前主流的工艺是130 nm和90 nm,所面临的静电放电(ESD,Electro Static Discharge)挑战也越来越严峻.基于ESD研究背景,ESD故障机制和放电模型,ESD器件保护以及器件在布局上的ESD性能,对设计的ESD器件进行TLP实测,得出的结论在芯片的ESD设计中具有重要的参考意义.

In this paper, we propose a mechanically reconfigurable coding metasurface for wavefront manipulation to modulate the scattering beams as desired. The phase pattern on the coding metasurface can be harnessed by mechanically adjusting the thickness of the air substrate using four precise stepper motors. When the coding metasurface is illuminated with a plane wave, the magnitude of the scattering beams can be manipulated as desired. In addition, by applying specific coding series, different radiation modes of the coding metasurface can be realized by mechanical manipulation. To realize these functionalities, a square patch unit cell with an air substrate is employed here. The metallic patterns of metasurfaces are fabricated via Flexible Printed Circuit (FPC) technology, whose inherent property is conformality, implying a broader range of potential applications. To demonstrate our schemes, three metasurface patterns are designed and simulated. Two of them are fabricated and measured, showing good agreement with our simulations. Compared with other methods of tunable coding metasurfaces, the mechanically coding metasurface yields lower system complexity, lower cost, and easier fabrication. Besides, flexibility, the intrinsic specialty of FPC, enables the proposed metasurface unparalleled applications, such as security imaging, medical sensing, and various wearable devices.

In this paper, a dual-functional tunable coding metasurface is presented at X band based on water substrate, which can realize two different functions of specific scattering pattern and absorption at two different frequency ranges. Besides, by changing the salinity of the saline water substrate, the absorption performance in high frequency can be tuned, while the scattering pattern in low frequency remains unchanged. A coding element is designed with small water cavity in it. Three coding sequences with different radiation patterns are designed to verify these functions, and one of them is fabricated and measured. Experimental results have good accordance with our simulations, which demonstrates our schemes. We believe this work can not only broaden our design manner of metasurfaces, but also have plenty potential applications in biological and medical detection domain.

针对物联网IoT的小面积低噪声的需求,相对传统共源共栅结构的低噪声放大器,提出了一种新型低噪声放大器.核心电路没有采用传统的源级电感负反馈的共源共栅结构,通过去除片上电感的方法,节省了77％的芯片面积.芯片采用IBM 0.18 μ m SiGe BiCMOS工艺设计制造.测试表明,电源电压在2.5 V情况下,在2.4 GHz处能够提供20 dB的前向增益,噪声系数为1.8dB,输入和输出匹配都小于-16 dB,1 dB压缩点为-15 dBm,消耗电流为3.6 mA,而芯片面积仅为0.45 mm×0.5 mm.

A wideband low-noise amplifier (LNA) with ESD protection for a multi-mode receiver is presented. The LNA is fabricated in a 0.18-μm SiGe BiCMOS process, covering the 2.1 to 6 GHz frequency band. After optimized noise modeling and circuit design, the measured results show that the LNA has a 12 dB gain over the entire bandwidth, the input third intercept point (IIP3) is −8 dBm at 6 GHz, and the noise figure is from 2.3 to 3.8 dB in the operating band. The overall power consumption is 8 mW at 2.5 V voltage supply.

A 1.8 V 5.2 GHz LNA with ESD protection for WLAN 802.11a was implemented in IBM 0.18 μm CMOS process.The LNA was optimized based on the analysis of input impedance,voltage gain and noise figure of cascode LNA with inductive degeneration.Effects of ESD protection on LNA performance were discussed.Test results showed that the LNA had a forward gain of 10 dB,a noise figure of 4.29 dB,an IIP3 of 4 dBm and an S11 of-18 dB,and the circuit dissipated 6.5 mA of current from 1.8 V supply.

A low phase noise VCO(voltage controlled oscillator)for single chip UHF RFID Reader is proposed.The regulator and filtering technology are adopted in order to suppress the noise from VDD and shot the second harmonic of current source for phase noise reduction in 1/f3 region.Meanwhile,proper L with a relative better Q value is chosen to improve phase noise in 1/f2 region.Low noise bandgap is also added in the propose VCO.The VCO is implemented using UMC0.18 μm MM/RF CMOS technology.Compared with the traditional VCO,simulation result shows the phase noise reduction is around 5 dB in all frequency regions.The center frequency of proposed VCO is 1.8 GHz with the tuning rage of 11% while the power consumption is 7.2 mA at 3.3 V.The VCO has phase noise of-127 dBc/Hz@1 MHz.

A transmitter front-end circuit applied in the portable UHF RFID reader is designed and fabricated in 0.18 μm CMOS process. The designed active I/Q up-mixer can realize all three modulation schemes specified in EPC Global Class-1Gen-2 protocol by switching the input signals of Q branch. With the realization of seven-class digitally adjustable conversion gain,the driver amplifier can effectively pre-amplify the output signals of up-mixer. Measured at 1.8 V power supply,the major performance parameters of the transmitter front-end circuit are described as follows:the up-mixer achieves-14.9 dB Vrmsinput-referred P1 dB,3.18 dB conversion gain and 13.20 dB NF,and the DA features 3.5 dBm output-referred P1 dB at 50 Ω,7.90～16.30 dB conversion gain variation,and 3.10～5.00 dB NF range.

A novel dual-band low noise amplifier applied in Wireless LAN is designed and fabricated in 0.18 μm CMOS process.In this dual-band LNA,by switching the input inductors and load inductors,the gain and impedance matching are achieved at the 2.4 GHz and the 5.2 GHz operation frequency bands,respectively.With a 1.8 V power supply,the LNA has a gain of 11.5 dB at 2.4 GHz and 10.2 dB at 5.2 GHz,and the noise figure of 3 dB at 2.4 GHz and 5.1 dB at 5.2 GHz,respectively.The total die area is 0.9 mm×0.65 mm.

According to requirements of EPC RFID Class-1 Generation-2 Protocols,a 3-order II-type charge pump phase locked loop(CPPLL) with a 250 kHz reference frequency was proposed,which acted as a frequency synthesizer for single-chip UHF RFID reader.The proposed CPPLL was implemented in MOSIS IBM 0.18 μm RF/MM CMOS technology.Post simulation results showed that the PLL had an output frequency ranging from 760 MHz to 1.12 GHz,and a phase noise of-113.1 dBc/Hz and-120.4 dBc/Hz at 250 kHz and 500 kHz offset,respectively,for 900 MHz operating frequency,while drawing 9.4 mA of current from a 3.3 V power supply.

A low phase noise CMOS LC VCO with prescaler for monolithic UHF RFID reader was proposed.A symmetrical filtration technology was adopted to suppress noise for complementary cross coupled LC VCO.Injection locked prescaler with ring oscillator core can provide wide locking range.Implemented with UMC 0.18 μm RF/MM CMOS technology, the proposed LC VCO covers a tuning range from 1.283 GHz to 2.557 GHz, and the prescaler has a locking range of 66.35% with in-phase and quadrature output.Test results showed that the PLL had a phase noise of -132.25 dBc/Hz at 3 MHz offset from 895.5 MHz, while drawing 8 mA of power from a 3.3 V supply.

A general purpose output Buffer with ESD for IO blocks of ASIC and FPGA is proposed in this paper.The output buffer is supplied by three power sources,and its driving ability can be exactly controlled by the digital signal so that it supports 16 selectable IO standards.The output Buffer and its ESD are implemented with SMIC 0.18 μm MM CMOS technology.The simulation results show that the output Buffer could be worked at 250 MHz for all IO standards and the transport lag is between 660 ps and 1180 ps.

A differential low noise amplifier applied in ASK receiver is designed and fabricated in UMC 0.18 ¿m CMOS process. The amplifier employs a differential cascode structure with source degeneration stage for single input and differential output, and avoids using balun when connected to mixer. This low noise amplifier has a measured forward gain of 18.2 dB and a noise figure of only 1.65 dB, thus can significantly improves entire receiver performance. Input and output matching is -28 dB and -24 dB, respectively, while input third-order intercept point (IIP3) is -9.8 dBm. The total power dissipation is 6.5 mW at 1.8 V supply and the die area is 0.6 mm × 0.9 mm.

A 433 MHz low noise amplifier applied in ASK receiver has been designed in UMC 0.18 μm standard CMOS process.The amplifier employs differential cascade structure with inductive source degeneration,implements single input and differential output,and avoids using balun when connect to mixer.This low noise amplifier provides a forward gain of 18.2 dB with a noise figure of only 1.65 dB,so this LNA can largely improves performance of receiver.Input and output matching is-28 dB and-24 dB,input third-order intercept point is-9.8 dBm.The total power dissipation is 6.5 mW from a 1.8 V supply.The LNA chip area is 0.6 mm×0.9 mm.

A 3.846GHz voltage-controlled oscillator based on IEEE 802.11 a/b/g is proposed,applied in the fist local oscillator of a RF receiver.The design is implemented by TSMC0.25μm RFCMOS process,and optimized by Hajimiri model.Performed by Cadence SPECTRE,the simulated power consumption is 10mW,the phase noises are-120dBc/Hz @1MHz,-131dBc/Hz @3MHz,respectively,and the frequency range by Vtune(0～2.5V) is 600MHz,which all above are completely meet the IEEE 802.11 a/ b/ g standards.

A wide locking range injection-locked prescaler based on CMOS ring oscillators in the 0.25-¿m CMOS process is described. The prescaler¿s free-running frequency is 1.47 GHz, and the locking range covers from 1 GHz to 2.4 GHz with in-phase and quadrature output. The prescaler dissipates 1.9 mA from a 3.3-V power supply.