The growing demand for efficient information processing in the era of AI and IoT urgently calls for neuromorphic hardware capable of alleviating the von Neumann bottleneck. Here, we report a Ti/Au/CuInP2S6/Ag/Au multi-mode memristor that naturally integrates three distinct resistive switching modes: volatile analog, volatile digital, and non-volatile digital. The volatile analog mode, driven by Cu-ion migration, naturally emulates leaky integrate-and-fire (LIF) neuronal dynamics. Meanwhile, Ag filament-based digital switching shows stochastic transitions between volatile and non-volatile states, tunable via compliance current. By directly mapping these switching modes onto core neuromorphic functions, a spiking neural network with built-in dropout is realized with drastically simplified circuit architectures. This work demonstrates how multi-mode memristive physics can unify neuron activation and dropout functionality within a single device, offering a compact and hardware-efficient pathway toward robust neuromorphic computing systems.

In micro/nanofabrication for integrated circuits and metastructures, fabrication errors can break structural symmetry and degrade device performance. For deep-subwavelength periodic structures, the antisymmetric characteristics are typically weak and easily buried by the strong background signals. Here, we propose an antisymmetric structure detection method based on orthogonally polarized back-focal-plane (BFP) imaging by collecting the zeroth-order diffraction from a deep-subwavelength target. The method suppresses the strong symmetric background signals and isolates the antisymmetric component using the 180° rotation differencing. Simulations of nanometer-scale overlay show that the antisymmetric signal induced by overlay errors can be detected and extracted under noisy conditions.

Oxide semiconductors have demonstrated unique advantages, including ultra-low leakage current and back-end-of-line (BEOL) compatible processing, for advanced memory applications such as three-dimensional (3D) dynamic random-access memory (DRAM). Nevertheless, detailed structural analyses and comprehensive feasibility evaluations remain limited. In this paper, a novel In-Ga-Zn-O (IGZO) 3D DRAM architecture is presented, featuring a gate-all-around (GAA) nanosheet (NS) transistor, vertical bit line (BL), horizontal word line (WL), WL staircase, and a 3D NAND-like fabrication flow based on industry-mature processes. A thorough investigation of parasitic effects is conducted, including parasitic bit-line capacitance $(\boldsymbol{C}_{\text{BL}})$ and a robust sensing margin. WL-related analysis shows that a 256-bit-long WL results in an RC delay of 2.4 ns, which is comparable to commercial Si-based counterparts. Furthermore, optimization of the interlayer dielectric (ILD) thickness, spacer width, and WL shape is employed to further suppress the WL RC delay to 1.5 ns. These results demonstrate the strong practical potential of the proposed IGZO-based 3D DRAM design. Further analysis show that a high bit density of over $1.3 \text{Gbit} / \text{mm} 2$ will be achieved for the IGZO 3D DRAM with 400-layer and 1024bit WL configuration.

The increasing demand for processing large volumes of data for machine learning (ML) models has pushed data bandwidth requirements beyond the capability of traditional von Neumann architecture. In-memory computing (IMC) has recently emerged as a promising solution to address this gap by enabling distributed data storage and processing at the micro-architectural level, significantly reducing both latency and energy. In this article, we present In-Memory comPuting architecture based on Y-FlAsh technology for Coalesced Tsetlin machine inference (IMPACT), underpinned on a cutting-edge memory device, Y-Flash, fabricated on a 180 nm complementary metal oxide semiconductor (CMOS) process. Y-Flash devices have recently been demonstrated for digital and analogue memory applications; they offer high yield, non-volatility and low power consumption. IMPACT leverages the Y-Flash array to implement the inference of a novel ML algorithm: coalesced Tsetlin machine (CoTM) based on propositional logic. CoTM utilizes Tsetlin automata (TA) to create Boolean feature selections stochastically across parallel clauses. IMPACT is organized into two computational crossbars for storing the TA and weights. Through validation on the MNIST dataset, IMPACT achieved 96.3 % accuracy. IMPACT demonstrated improvements in energy efficiency, e.g. factors of 2.23 over CNN-based ReRAM, 2.46 over neuromorphic using NOR-Flash and 2.06 over DNN-based phase-change memory (PCM), suited for modern ML inference applications. This article is part of the theme issue ‘Emerging technologies for future secure computing platforms’.

Memristor-based analog in-memory learning (AIML) has emerged as a promising approach to improve energy efficiency in deep neural network training. However, non-idealities in memristive devices, such as nonlinearity, asymmetry, and cycle-to-cycle (C2C) and device-to-device (D2D) variations, pose significant challenges. These issues lead to increased energy consumption, reduced write precision, and compromised in-situ learning performance. To address these problems, we propose a mixed-precision training strategy that combines gradient accumulation with single pulse blind write method. We analyze the failure mechanisms of in-situ learning without these techniques and systematically investigate how various non-idealities affect AIML performance. We demonstrate that, by using our GA-Single Pulse strategy, high accuracy (95.36%) can be achieved even under significant non-idealities, including device conductance states being limited to 10 pulses for potentiation as well as 5 pulses for depression, the asymmetry of conductance state constrained to a factor of 2, the nonlinearity in long-term potentiation/ long-term depression curve reaching up to 5, C2C variation as high as 50%, and D2D variation extending up to 40% for learning handwritten digits in MNIST handwritten digit dataset, outperforms all previous reports. The results suggest that the idealities of memristive devices may not be as critical as previously assumed for AIML's practical deployment.

With the rapid development of artificial intelligence (AI) technologies, the demand for data storage and neuromorphic in-memory computing has been increasing. Ferroelectric field effect transistors (FeFETs) that couple semiconductors with functional ferroelectrics hold great promise for overcoming the bottlenecks of the von Neumann architecture. A laterally gated FeFET (LG-FeFET) employs an in-plane electric field to switch the out-of-plane polarization, offering the benefit of low leakage current and reduced device height for device integration. Here, we demonstrate two-dimensional (2D) laterally gated FeFET (LG-FeFET) devices utilizing ferroelectric CuInP2S6 (CIPS) and MoS2 semiconductors in a van der Waals (vdW) heterostructure, exhibiting multilevel data processing capabilities and tunable synaptic functions. The 2D LG-FeFET exhibits a large memory window (10 V), low leakage current (<0.01 nA), and a large on/off ratio (105), dramatically outperforming the vertical gate FETs. The device successfully emulates the synapses' plasticity under electric stimuli, including long-term and short-term plasticity. Our in situ piezoresponse force microscopy (PFM) measurement confirms that the multiple conductance states in 2D LG-FeFET devices are directly controlled by the polarization evolution dynamics. Furthermore, using this synaptic device for online training of a neural network for recognition of handwritten digits, a high recognition accuracy (97.4%) is attained. Finally, based on the short-term plasticity of the device, we demonstrated reservoir computing for image classification. Our results show that the LG-FeFET device holds great promise for high-density data processing systems and neuromorphic computing applications.

Nanofluidic memristors provide an unprecedented platform for neuromorphic computing by ionic conductance switching through hydrated ion transport dynamics and ion redistribution within nanochannels. Herein, we present a three-terminal field-effect nanofluidic memristor with gate-controlled ionic transmission that enables multidimensional reconfiguration of memristive characteristics, emulating both structural and functional features of voltage-gated biological ion channels. Through phase-modulated gate pulses, we achieve programmable frequency-adaptive pinched hysteresis with loop area scaling, quadrant-selective orientation, bidirectional hysteresis polarity, and low-pass filtering properties. Critically, the device emulates bio-synaptic plasticity at low-level energy consumption per spike. This work establishes an electrostatically gated neuromorphic platform for adaptive learning, suggesting nanofluidic field-effect transistors as feasible blocks for energy-efficient neuromorphic systems.

Integrating spintronic devices onto flexible substrates has been demonstrated to offer new opportunities for flexible electronics. For instance, spintronics-based electronic skins enable humans to perceive and interact with magnetic fields. Beyond their advantages of low power consumption and high endurance, spintronic devices possess intrinsic brain-like computing capabilities, which, however, remains underexplored in flexible electronics. Here, we develope a spintronic neuromorphic device with inherent thermally activated relaxation and nonlinear spin-orbit torque switching behaviors, realizing the nonlinear response and fading memory requirements for reservoir computing. The device demonstrates powerful capabilities in accurately recognizing sensing signals from wearable devices, and the results pave the way for the development of next-generation intelligent and efficient wearable devices and e-skins.

The separation of "storage and computation" in the traditional von Neumann architecture creates an insurmountable "memory wall" bottleneck, resulting in high energy consumption and low data transfer efficiency. The integration of brain-like functions that combine sensing, storage, and computation into a unified hardware system has emerged as a promising strategy for overcoming the von Neumann limitations. This study presents a comprehensive investigation into the development of an integrated optoelectronic neuromorphic system based on tellurium oxide (TeOx) memristor for artificial vision applications. The TeOx memristor exhibits excellent resistive switching (RS) properties and achieves synaptic plasticity and OR, AND logic gates under light and electrical stimulation. Modulated by light pulses with different wavelengths, it mimics associative learning and the brain's "melatonin secretion and inhibition" process. Furthermore, the short-term plasticity and long-term plasticity demonstrated by the device can mimic the function of visual neural networks in recognizing and memorizing images from noise. By further integrating the synaptic plasticity functionality with a convolutional neural network (CNN), the device is capable of achieving precise image recognition and classification, with an accuracy of 94.84%. This indicates the significant potential of optoelectronic devices based on TeOx in the field of artificial vision applications.

The ionic transportation process is the main driving mechanism in novel microelectronic devices, such as resistive random access memories (RRAMs) and ionic-gated transistors. Understanding the ionic migration under multiple coupled physical fields provides valuable information and guidelines for device design and optimization. The oxygen vacancies transportation processes include drift under an electric field, Fick diffusion under a concentration gradient, and Soret diffusion or thermophoresis under a temperature gradient, where the last effect is often neglected. The working mechanism of RRAM devices depends on the conductive filament formation and rupture inside the resistive switching (RS) layer. The reliability and uniformity issues of RRAM devices come from the complex ionic transportation in amorphous materials under multiple coupled physical fields. In this work, we propose a technology computer-aided design (TCAD) model for RRAM devices that includes the full ionic transport mechanisms as well as takes the ionic generation and recombination processes into consideration. Based on this model, we investigated the effect of different parameters on device behavior.

Two-dimensional (2D) van der Waals (vdW) ferroelectric (FE) materials have recently emerged as promising candidates for advanced synaptic devices in brain-inspired neuromorphic computing systems. These materials retain ferroelectricity down to a few atomic layers, including the monolayer limit. Their unique properties-such as atomically clean surface/interface, mechanical flexibility, and LEGO®-like stacking capability-offer significant advantages for complementary metal-oxide-semiconductor (CMOS)-compatible fabrication, enabling high integration density, energy-efficient operation, and fast switching speed. Importantly, the intrinsic polarization in 2D ferroelectrics can couple with various physical phenomena, enabling the emulation of complex biological synaptic behaviors. This review provides a comprehensive overview of recent advances in 2D ferroelectric-based synaptic devices, with a particular focus on the role of coupling mechanisms within these materials. Firstly, we introduce the principles of neuromorphic computing, and advantages of 2D ferroelectric materials. Next, we classify 2D ferroelectric materials according to five key types of coupling mechanisms. We then review representative studies on 2D FE-based synaptic devices by analyzing how each coupling mechanism is utilized to achieve synaptic functionality. Finally, we discuss current challenges and prospects for leveraging these coupling mechanisms in synaptic applications. The purpose of this review is to provide a structured understanding of how intrinsic coupling in 2D ferroelectric materials can be utilized for the design of high-performance and biologically inspired synaptic devices.

3D integration with thinned memristor dies or wafers enables energy-efficient and lower-latency computing in data-intensive applications. However, mechanical stresses induced by warping, bonding, and interconnects during stacking package can critically impact device reliability. Despite this, in-chip mechanical reliability characterization and modeling for memristor-based chip for 3D integration remain unexplored, limiting their practical deployment. Here, a comprehensive study is performed on the in-chip mechanical reliability of memristors based on a thinned complementary metal-oxide-semiconductor (CMOS)-integrated memristor chip. Chip-level statistical analysis demonstrates that outward mechanical stress can regulate ion/oxygen vacancy migration in conductive filaments, thus affecting forming voltage, SET/RESET voltages, and retention properties. A comprehensive mechanical stress-related model is further developed to quantify reliability degradation of the memristor chip and evaluate its impact on in-memory computing. These findings provide a new insight into the mechanical reliability of CMOS-integrated memristor chip for 3D integration.

In this work, the requirement of using high‐precision (HP) signals is lifted and the circuits for implementing deep learning algorithms in memristor‐based hardware are simplified. The use of HP signals is required by the backpropagation learning algorithm since the gradient descent learning rule relies on the chain product of partial derivatives. However, it is both challenging and biologically implausible to implement such an HP algorithm in noisy and analog memristor‐based hardware systems. Herein, it is demonstrated that the requirement for HP signals handling is not necessary and more efficient deep learning can be achieved when using a binary stochastic learning algorithm. The new algorithm proposed in this work modifies elementary neural network operations, which improves energy efficiency by two orders of magnitude compared to traditional memristor‐based hardware and three orders of magnitude compared to complementary metal–oxide–semiconductor‐based hardware. It also provides better accuracy in pattern recognition tasks than the HP learning algorithm benchmarks.

Advancements in the semiconductor industry introduce novel channel materials, device structures, and integration methods, leading to intricate physics challenges when characterizing devices at circuit level. Nevertheless, accurate models for emerging devices are crucial for physics-driven TCAD-to-SPICE flows to enable the increasingly vital design technology co-optimization (DTCO). Particularly for ultra-scaled devices where quantum effects become significant, this led to the introduction of empirical model parameters and a disconnection to manufacturing processes. To catch up with these developments, an alternative to the traditional white-box modeling methods has attracted much attention: machine learning-assisted compact modeling (MLCM). These black-box methods target towards general-purpose modeling of complex mathematics and physics through training of neural networks on experimental and simulated data, generating an accurate closed-form mapping between output characteristics and input parameters for fabrication process and device operation. To address this new trend, this work provides a comprehensive overview of emerging device model methodologies, spanning from device physics to machine learning engines. By analyzing, structuring, and extending distributed efforts on this topic, it is shown how MLCM can overcome limitations of traditional compact modeling and contribute to effective DTCO to further advance semiconductor technologies.

Crossbar arrays of memristors are promising to accelerate the deep learning algorithm as a non-von-Neumann architecture, where the computation happens at the location of the memory. The computations are parallelly conducted employing the basic physical laws. However, current research works mainly focus on the offline training of deep neural networks, i.e. only the information forwarding is accelerated by the crossbar array. Two other essential operations, i.e. error backpropagation and weight update, are mostly simulated and coordinated by a conventional computer in von Neumann architecture, respectively. Several different in situ learning schemes incorporating error backpropagation and/or weight updates have been proposed and investigated through neuromorphic simulation. Nevertheless, they met the issues of non-ideal synaptic behaviors of the memristors and the complexities of the neural circuits surrounding crossbar arrays. Here we review the difficulties and approaches in implementing the error backpropagation and weight update operations for online training or in-memory learning that are adapted to noisy and non-ideal memristors. We hope this work will be beneficial for the development of open neuromorphic simulation tools for learning-in-memory systems, and eventually for the hardware implementation of such as system.

NbOx-based devices exhibit intriguing promise for beyond-CMOS applications due to their dynamic threshold switching (TS) and negative differential resistance (NDR) behaviors. However, an in-depth study on the degradation scheme of such a device is absent. In this work, we investigate the degradation behavior, i.e., the shift of switching voltages ( ${V}_{\text {th}}$ , ${V}_{\text {hold}}$ ) and the shrink of voltage window (VW), of a nanoscale forming-free TiN/NbOx/TiN memristor. Through electrical tests and random telegraph noise (RTN)-based defect tracking, we proved that the shrink of the VW and the increase of switching voltages originate from the increase of electrode resistance due to the oxygen vacancy accumulation. According to the elucidated degradation mechanisms, we propose a reverse refresh strategy to extend the endurance and delay VW degradation. This work provides a possible view of NbOx devices’ degradation and may promote the applications.

In this paper, a novel smooth magnetron is introduced to construct a fractional memristor Hopfield neural network (fractional order M-HNN). The local stability of equilibrium point are analyzed theoretically. Taking the memristor coupling strength coefficient and the fractional order as bifurcation parameters, the phase trajectory diagram, the bifurcation diagram of the system are drawn to analyze the influence on the dynamic behavior of the neural network. When the system parameters are fixed, the hyperchaos phenomenon of the fractional order M-HNN model is revealed. Finally, the PD controller is applied to the model to enhance the stability of the system.

Resistive switching devices herald a transformative technology for memory and computation, offering considerable advantages in performance and energy efficiency. Here we employ a simple and scalable material system of conductive oxide interfaces and leverage their unique properties for a new type of resistive switching device. For the first time, we demonstrate an Al_2O_3-TiO_2 based valence-change resistive switching device, where the conductive oxide interface serves both as the back electrode and as a reservoir of defects for switching. The amorphous-polycrystalline Al_2O_3-TiO_2 conductive interface is obtained following the technological path of simplifying the fabrication of the two-dimensional electron gases (2DEGs), making them more scalable for practical mass integration. We combine physical analysis of the device chemistry and microstructure with comprehensive electrical analysis of its switching behavior and performance. We pinpoint the origin of the resistive switching to the conductive oxide interface, which serves as the bottom electrode and as a reservoir of oxygen vacancies. The latter plays a key role in valence-change resistive switching devices. The new device, based on scalable and complementary metal-oxide-semiconductor (CMOS) technology-compatible fabrication processes, opens new design spaces towards increased tunability and simplification of the device selection challenge.