We report the fabrication of modulation doped Si/Gex Si1−x heterostructures by molecular beam epitaxy. The samples are characterized by Rutherford backscattering spectrometry, cross-sectional transmission electron microscopy, electron beam induced current, Hall measurement, and the magnetoresistance (Shubnikov-de Haas) measurements. Threading dislocation densities of = 106cm−2 are observed for relaxed Ge0.3Si0.7 films on Si (100). The modulation doped structures fabricated on these Ge0.3 Si0.7 films contain two-dimensional electron gases with mobilities ranging from 60,000 to 96,000 cm2/V - s at 4.2 K.

In order to design competitive circuits in finFET technologies, a designer must intelligently navigate the plethora of reliability rules, As an example, by understanding the trade-offs between transistor self-heating, Joule-heating due to Irms currents and passing Iavg rules at higher temperatures, designers can optimize the design changes required to meet overall interconnect reliability requirements. In addition, accounting for appropriate levels of Bias Temperature Instability (BTI) and Hot-Carrier Injection (HCI) aging during timing closure requires knowledge of the critical path behavior and interactions. Furthermore, voltage limits based on time-dependent-dielectric breakdown (TDDB) for gate-dielectrics can be tailored based on total area exposed to a given voltage. A Design-for-Reliability (DFR) methodology is presented, which prevents over-design by accounting for accurate mission-mode operation, and enables improvements in performance, and reduction of area, along with Si-based validation of robustness with respect to aging.

The greatest benefits of nitrogen incorporation into gate dielectrics may be obtained by placing nitrogen preferentially at the interfacial regions of the dielectric film. One method of distributing nitrogen in this manner is by using a three-step thermal process consisting of 1.) oxynitridation in NO, 2.) subsequent reoxidation in O-2, and 3.) a final NO anneal. This study investigates the effect of NO processing on substrate/dielectric interface roughness and correlates that roughness with dielectric reliability. The initial NO-containing step can roughen the interface, as can subsequent reoxidation. Increased NO exposure yields a greater nitrogen content and a concomitant increase in interface roughness. These films show a degradation in charge to breakdown (Q(bd)) of at least an order of magnitude when compared with similarly prepared O-2-oxide films. An O-2/NO process produces films with interface roughness and Qbd comparable to that of pure SiO2, independent of nitrogen content. The oxynitride reliability depends on the exact scheme for incorporating nitrogen into SiO2.

Non-alloyed refractory ohmic contacts to P+-ln0.53 Ga0.47 As layer have been fabricated using sputtered W and rapid thermal processing. These contacts showed excellent thermal stability over the temperature range of 300 to 750°C, with an abrupt and almost unreacted metal-semiconductor interface. The W film biaxial stresses were found to be strongly depended on the Ar pressure during the sputter deposition. At low Ar pressures the film were deposited with compressive stress, and became tensile at pressures higher than 7mTorr with a maximum value of about 8×l09 dyne cm2 as a result of Ar deposition pressure of 28mTorr. The W contacts to Zn doped 1×1019 cm−3 In0.53GA0.47 As film was found to be ohmic already as deposited with a minimum specific resistance of about 7.5×10−6 Ωcm−2, achieved as a result of heating at 600°C for about 30 sec.

We develop a novel approach for hot carrier lifetime prediction based on the `universality of HCI degradation' that not only generalizes the classical theory by obviating the measurement of I B , but also allows prediction of HCI lifetime over a broad range of technology nodes, bias conditions, and device geometries. We explain the shape of the degradation vs. time characteristic based on the energy distribution of the Si-O bonds, and we show, based on the bond-dispersion model, that the degradation shows similar features for both ON- and OFF-state bias conditions.

Transmission line pulse (TLP) measurements are used to demonstrate that oxynitride breakdown projections from DC measurements using conventional area and voltage-scaling techniques can be extended to the nanosecond time-scale. ESD protection systems can thus be designed to prevent dielectric breakdown. Important concepts in gate dielectric breakdown such as the anode–hole injection model and area and statistical effects are discussed and applied to the nanosecond regime.

A theory of the current-ratio technique, which is widely used to locate gate oxide breakdown spots in one dimension (i.e., distance from source or drain), is proposed and verified. The theory shows that the current-ratio method is a special case of generalized van der Pauw technique, and as such, can easily be generalized to locate oxide breakdown spots in two dimensions. We develop the theoretical framework of this new class of breakdown-spot characterization techniques and then validate the theory by experiments. We conclude by discussing the implications of locating breakdown spots in two dimensions for reliability projections of ultra-thin gate oxides

The challenge of electrostatic discharge (ESD) design is that as scaling continues and operating voltages are lowered, the interface to the outside world and therefore the ESD specifications remain the same. Moreover, as has been highlighted by Duvvury et al. (1996), the first breakdown voltage for snapback of a transistor and the median breakdown voltage of the gate dielectric are converging, making it difficult to ensure the robustness of gate dielectrics in an ESD event. This is particularly true for 1V I/O's in high-speed, high-performance applications, where transistor gates may be directly connected to an external pin or NFETs may be used as compact decoupling capacitors between VDD and VSS, exposing the thin gate dielectric to ESD stress. The ESD protection and interconnects can both contribute voltage drops during an ESD pulse, and their sum must not be higher than the voltage which a dielectric can withstand. Especially alarming is the fact that in the sub-2nm regime, significant statistical variation exists as well as a dependence on area for dielectric breakdown. A vast knowledge base exists for oxide breakdown in the long time-scale, and a few publications have addressed short time-scales. For the most part, studies which described breakdowns at short times have used methodology developed for thicker oxides. In the case of thinner oxides or oxynitrides, the voltage acceleration is no longer 1/E, the dielectric breakdown voltage depends sensitively on the dielectric area, and small differences in thickness have a significant effect on the dielectric breakdown voltage. Therefore, the purpose of this paper is to study the relevance of long time-scale TDDB data in predicting the response to short time-scale ESD events, especially for sub-2nm dielectrics in both NFETS and PFETS.