We report a first demonstration of GaAs HBT-OI fabricated using epitaxy growth, wafer bonding and layer transfer technique. Excellent bonding yield was found on the 200 mm GaAs HBT-OI wafer with wafer bowing of less than 90 & mu;m. A dc gain of 20, and cutoff frequency (fT) of 6.5 GHz was measured for a device with emitter finger of 6 x 18 & mu;m2. Its ideality factors for collector and base were 1.19 and 1.44, respectively. These results showed that the method of GaAs HBT-OI fabrication can be used for future integration of III-V on a common Si platform with low RF power dielectric attenuation.

Designing the next generation of high-resolution displays requires high pixel density per area and small pixel sizes without compromising the optical quality. Quantum dots (QDs) have been demonstrated as a promising material system for down-conversion of blue emission as they provide pure colors on the wide color gamut. However, for high color-conversion efficiency, the required QD film thickness has not been compatible with small pixel sizes. In this work, we develop a new type of freestanding QD-based color converter for efficient optical down-conversion from inorganic blue light-emitting diodes (LEDs) in a color-by-blue configuration. CdSe/ZnS core-shell QDs in a UV-curable polymer matrix are encapsulated within cavities formed by patterning and bonding a pair of patterned quartz substrates. By controlling the required QD thickness and the pixel size independently, we demonstrate freestanding monochrome red and green converters with small pixel sizes down to 5 × 5 μm2 and a high resolution of >3600 ppi. The optical studies show that the QD film thickness required for efficient color conversion can be successfully realized even for the small pixel sizes. We further combine green and red pixels in a single converter to achieve white emission when combined with blue LED emission. The QD color converter design and processing are decoupled from the LED fabrication and can be easily scaled to wafer-size integration with arbitrary pixel sizes for QD-based RGB displays with ultrahigh resolution.

A wideband millimeter-wave phase shifter is designed and fabricated in 0.15 µm Gallium Arsenide (GaAs) high electron mobility transistor (HEMT) technology. It operates from 20 GHz to 28 GHz with 5 dB insertion loss and provides 70 degrees phase change between ON and OFF modes with 4 % phase error within the frequency range. The DC and small signal model of the GaAs HEMT is calibrated and validated in the phase shifter simulation against measurement. The designed phase shifter occupies only 0.42 mm2 including DC bias circuitry, which can be integrated together with mid- and low-power GaAs amplifiers in a phased array system for 5G millimeter-wave communications.

We report an In0.3Ga0.7As HBT device grown on a 200 mm Si wafer using GeSi as virtual starting substrate and InAlAs as the compositionally graded buffer layer from GaAs to In0.3Ga0.7As lattice constant. A DC gain, emitter base, and base-collector ideality factors of 10, 1.43, and 1.56, respectively, are obtained for a device with an emitter area of 40 x 50 mu m(2). Small-signal simulation of an In0.3Ga0.7As HBT device with 2 x 8 mu m2 emitter area shows that current gain cutoff frequency (fT) and maximum cut-off frequency (fMax), of 50 GHz and 220 GHz, respectively, can be achieved with base doping and layer thickness of 2 x 10(18)cm(-3) and 30 nm, respectively.

Realization of fully solid-state white light emitting devices requires high efficiency blue, green, and red emitters. However, challenges remain in boosting the low quantum efficiency of long wavelength group-III-nitride light emitters through conventional quantum well growth. Here, we demonstrate a new direct metal-organic chemical vapor deposition approach to grow In-rich InGaN quantum dots on Si substrates using V-pits, bypassing the need for patterning or unconventional substrates. A correlative nanoscale study on the optical, compositional, and structural properties of intersecting V-pits reveals that the highly textured surface gives rise to localized high intensity red-shifted emission from the apexes of pyramids where InGaN quantum dots spontaneously form. We establish the origin of this efficient long wavelength luminescence to result from both spatially confined higher In-content deposition, as well as smaller bandgap energy basal stacking faults entrapped within a ring of low-emissivity prismatic stacking faults. Our monolithic growth approach on Si would open up new pathways toward attaining CMOS-compatible phosphor-free white light emitting solid-state devices.

In this article, we demonstrate the Ti/TiN/Al (15/50/50 nm) ohmic contact on InGaP/GaAs heterojunction bipolar transistors (HBTs) epitaxially grown on 200-mm Si substrate. We study the rapid thermal annealing (RTA) effect of the metal stack on both n-type InGaAs and p-type GaAs. The dc characteristics of the HBT devices fabricated using the Ti/TiN/Al metal contacts have been analyzed. Contact resistances ${(}{R}_{c}{)} < 0.1~\Omega \cdot $ mm for n-InGaAs and $0.8~\Omega \cdot $ mm for p-GaAs can be achieved. A dc current gain of 45 with a collector–base breakdown voltage (BV cbo ) of 15.65 V is achieved. The ideality factor of the emitter–base current ( ${n}_{b}$ ) and base–collector current ( ${n}_{c}$ ) is 1.03 and 1.44, respectively, after RTA at 450 °C. The dc characteristics remain stable upon prolonged annealing at 450 °C for 45 min. This high thermal budget non-gold ohmic contact is suitable for Si-CMOS integration and enables the potential for hybrid III-V CMOS technology for 5G and mm-wave applications.

The heterogeneous integration of III–V devices with Si-CMOS on a common Si platform has shown great promise in the new generations of electrical and optical systems for novel applications, such as HEMT or LED with integrated control circuitry. For heterogeneous integration, direct wafer bonding (DWB) techniques can overcome the materials and thermal mismatch issues by directly bonding dissimilar materials systems and device structures together. In addition, DWB can perform at wafer-level, which eases the requirements for integration alignment and increases the scalability for volume production. In this paper, a brief review of the different bonding technologies is discussed. After that, three main DWB techniques of single-, double- and multi-bonding are presented with the demonstrations of various heterogeneous integration applications. Meanwhile, the integration challenges, such as micro-defects, surface roughness and bonding yield are discussed in detail.

We report the fabrication of modulation doped Si/Gex Si1−x heterostructures by molecular beam epitaxy. The samples are characterized by Rutherford backscattering spectrometry, cross-sectional transmission electron microscopy, electron beam induced current, Hall measurement, and the magnetoresistance (Shubnikov-de Haas) measurements. Threading dislocation densities of = 106cm−2 are observed for relaxed Ge0.3Si0.7 films on Si (100). The modulation doped structures fabricated on these Ge0.3 Si0.7 films contain two-dimensional electron gases with mobilities ranging from 60,000 to 96,000 cm2/V - s at 4.2 K.

SiGe films were grown on a chemical vapor deposition (CVD)-grown Si0.88Ge0.12 /Si (0 0 1) graded film with different growth solution compositions using a temperature interval of 950-940 degrees C by liquid phase epitaxy (LPE). The LPE films grown on the CVD-grown SiGe/Si (0 0 1) graded film are >= 86% relaxed, much more relaxed than those on bare Si (Wang and Quitoriano, 2019) since the existing threading dislocations in the CVD-grown SiGe/Si (0 0 1) graded film glide to create misfit dislocations without needing to nucleate new ones. The threading dislocation density of the LPE films is slightly lower than that of the CVD-grown SiGe films and on the same order of magnitude, similar to 10(6) cm(-2). Since the CVD-grown SiGe/Si (0 0 1) graded film was annealed for 4 h before the LPE growth occurred, the properties of the CVD-grown SiGe/Si (0 0 1) graded film were studied and we found that the CVD-grown SiGe/Si (0 0 1) graded film have SiGe islands appear all over the surface aligned along the <1 1 0> crosshatch morphology and become more relaxed after annealing.

N-p-n InGaP/GaAs double heterojunction bipolar transistor has been successfully grown on a 200 mm Ge/Si wafer using metalorganic chemical vapor deposition with low defect density of 107 cm-2. Non-gold metals of Ni/Ge/Al and Ti/Al are used to form the ohmic contact for small pieces device fabrication. Both direct-current (dc) and high-frequency characteristics of the device were measured. The device with emitter area of 6 × 8 μm2 shows a dc gain of 55 at a collector current of Ic = 4 mA, with high collector-emitter breakdown voltage of ~17 V. The high-frequency response with cutoff frequency (fT) of 23 GHz and maximum available frequency (fmax) of 10 GHz can be achieved. These results demonstrate that InGaP/GaAs double heterojunction bipolar transistor grown on low defect density Ge/Si wafer has the potential for realizing III-V CMOS integrated platform for high-frequency applications.

This paper presents a logic inverter circuit consisting of both CMOS and GaN devices to drive high-torque DC motors requiring high voltages in various robotics applications. The GaN+CMOS inverter can be monolithically integrated with CMOS digital circuits on a single die, accommodating a 5V CMOS logic level input and providing a 30V output voltage using depletion-mode GaN HEMTs without negative gate bias circuitry. Electro-thermal simulations are also performed to analyze the temperature of CMOS devices affected by nearby GaN HEMTs.

Low threading dislocation density (TDD) in GaAs epitaxial layers grown on silicon substrate (e.g. TDD < 106 cm−2) is critical for GaAs-based optoelectronic and high-performance electronic devices on silicon. Ge buffers and InxGa1-xAs/GaAs superlattice layers (SLs) are commonly used to reduce the TDD in GaAs epitaxial layers grown on Si wafers. In previous reports, TDD of ~107 cm−2 in GaAs and InGaP layers grown on 200 mm Si wafers was achieved by using Ge buffers only (e.g. Wang et al 2017 Semicond. Sci. Technol. 32 125013) and TDD of ~106 cm−2 in GaAs epi-layers for quantum dot lasers on Si was achieved by using SL insertion layers (e.g. Shang et al 2019 IEEE J. Sel. Top. Quantum Electron. 25 1502207). In this work, the effectiveness of the dislocation filtering effect of InxGa1-xAs/GaAs SLs combined with Ge buffers is investigated. The results are compared with wafers where InxGa1-xAs/GaAs SLs were directly grown on GaAs-on-Si buffers without Ge buffers. The InxGa1-xAs/GaAs dislocation filter layers (DFLs) consisted of 10 nm InxGa1-xAs/10 nm GaAs layers superlattice spaced by GaAs layer. Then, 1000 nm thick InGaP layers were grown on top of the DFLs to characterize the effect. Transmission electron microscopy, etch-pit density, x-ray diffraction, and photoluminescence were performed to characterize the quality of the materials. Our results indicate that for the growth with Ge buffers there was no significant difference in the final TDDs in the InGaP layers compared with a reference wafer that did not have DFL. For the growth without Ge buffers, the dislocation filtering effect was indeed observed, although it was not as significant as in other reports. For all wafers with DFLs, large wafer bow and dense film cracks appeared, which hinders the practical application of this method.

Si columnar structures were fabricated using Si MBE on Si substrates with column sizes in the order of − 100 Å The objective is to explore a viable approach to fabricate quantum wire structures. The growth of the structures, which was due to the growth instability, was an excellent example of a self-limiting process. The dependence of column morphology on the critical parameters, e.g., Si molecular beam incident angle, substrate temperature, substrate rotation, speed, etc., were demonstrated. Comparison between the experimental and the computer simulation results demonstrated the importance of the latent heat related atom migration as compared to the normal surface diffusion at low substrate temperatures and several A/s beam fluxes. A substrate temperature window (≈125°C) was observed which allowed the fabrication of crystalline micro-columns on Si (100) substrates. RHEED studies indicated that the crystalline micro- columns were heavily twined. The twinning phenomenon was also observed in the computer simulation results and interpreted as a result of the reduction in twin formation energy due to the extremely small dimension of the columns. Thermal stability of the columnar structures is discussed. Finally, photoluminescence studies and some potential applications are also discussed.

The needs of electronics are endless. The complexity in designing a circuit to meet high demand markets has increased daily. Furthermore, the urge for high power gain for high-efficiency RF applications leads to searching a replacement of Si material. III–V compound semiconductor (CS) materials provide a promising technology booster but integrating into the state-of-the-art Si equipment for VLSI faces some challenges for circuit designs and device fabrication. To ease the design complexity, Process Design Kit (PDK) has been widely used for modern semiconductor designs. This paper presents cross-platform III–V/Si circuit simulation, schematic and layout design, and integration of III–V/Si design verification for VLSI on 200-mm wafer in Si CMOS fabrication environment.

Speculations regarding electronic and photonic properties of strained germanium (Ge) have perpetually put it into contention for next-generation devices since the start of the information age. Here, the electromechanical coupling of <111> Ge nanowires (NWs) is reported from unstrained conditions to the ultimate tensile strength. Under tensile strain, the conductivity of the NW is enhanced exponentially, reaching an enhancement factor of ∼130 at ∼3.5% of strain. Under strains larger than ∼2.5%, the electrical properties of Ge also exhibit a dependence on the electric field. The conductivity can be further enhanced by ∼2.2× with a high bias condition at ∼3.5% of strain. Cyclic loading tests confirm that the observed electromechanical responses are repeatable, reversible, and related to the changing electronic band structure. These tests reveal the excellent prospects for utilizing strained Ge NWs in photodetector or piezoelectronic transistor applications, but significant challenges remain to realize strict direct band gap devices.

Integrate LEDs and CMOS circuits on large Si wafers can enable numerous new applications and add new functions to Si integrated circuits. In the past efforts on the integration of AlGaInP LEDs and CMOS circuits on 200 mm Si wafers, we have solved fundamental problems such as III-V semiconductor heteroepitaxy on Si substrates, wafer bow control, and bonding of LED wafers with CMOS wafers. Our latest achievement in this work is the demonstration of working devices processed on 200 mm LED wafers. We will present our efforts on the development of CMOS-compatible Ohmic contacts, 200 mm wafer-scale processing, and characteristics of the devices. We have evaluated different metals as CMOS-compatible low-resistance Ohmic contacts to the AlGaInP LEDs. We will compare the performance of the LEDs using the different metal contacts. We will present our progress on the process of CMOS-bonded LED wafers. Different from the LED-only wafers, the process of CMOS-bonded LED wafers can only be done in opened trenches, which adds extra difficulties. In addition, we will show the method we have developed for the re-entry of the CMOS-LED integrated wafers to the CMOS foundries for the end-of-line metal interconnections. Finally, potential applications using the CMOS-integrated LEDs will be discussed.

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafer, two issues need to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and create unbonded area. To address this, a CMP process that using conventional SiO 2 slurry with additional diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer to a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate is realized.

In this work, inductors and capacitors are designed and fabricated on an InGaAs-on-Insulator (InGaAs-OI) wafer that enables millimeter-wave (mmWave) integrated circuits design together with InGaAs high electron mobility transistors (HEMTs) for 5G mobile devices. Wafer bonding process between an InGaAs wafer and a high resistive substrate is developed and optimized for high frequency operation. Fabricated passive components are measured and compared against the electro-magnetic (EM) simulation data. A phase shifter circuit which is essential for directional beamforming in 5G mmWave communications is designed based on the measured data, which demonstrates the feasibility of integrated mmWave circuits design on an InGaAs-OI wafer for high data rates and small form factor 5G mobile devices.

One effective approach to reduce the cost of GaN devices is to use 200 mm-diameter and 725 μm-thick p-Si substrates. We demonstrated RF and power GaN-on-Si HEMTs on small pieces of samples from 200 mm wafers using Au-contained process. f T /$f_{\max}$ of 36/33 GHz were achieved in 0.25 μm gate RF devices and breakdown voltage (BV off )>1200V was achieved in power devices. 200 mm wafers were fabricated using CMOS-compatible process and devices with BV off >850 V were achieved.

To improve the bonding yield and the brightness of the final integrated Si-CMOS + GaN LED wafers, two issues have to be addressed. The first problem is the surface protrusions such as melt-back etching and hillocks which are the common surface imperfections on the surface of GaN/Si substrates. This prevents the direct contact of the two wafers and results in unbonded area. To address this, a CMP process that using conventional SiO2 slurry with the addition of diamond nanoparticles is carried out on the GaN (LED)-on-Si wafer prior to the bonding to the Si-CMOS wafer. The second issue is that the Si substrate of the GaN LED wafer absorbs photons which lowers the light emitting efficiency of the LEDs. We address this issue by transferring the Si-CMOS + GaN LED films from the Si (111) wafer onto a transparent quartz substrate. By addressing these issues, a high bonding yield and high brightness of Si-CMOS + GaN LED on quartz substrate can be realized.