Embedded systems are becoming increasingly complex, which has led to a productivity crisis in their design and verification. Although conventional design automation coupled with IP and platform reuse techniques have led to leaps in design productivity improvement, they face fundamental limits given that most design optimization and verification problems remain NP-hard and that reuse of pre-designed IP blocks and platforms inherently limits flexibility and optimality. At the same time, machine learning (ML) has recently made unprecedented advances and created phenomenal impact in various computing applications. In particular, application of ML techniques as a way to extract knowledge and learn from existing design, optimization and verification data has recently seen a lot of excitement and promise at lower physical and integrated circuit levels of abstraction. Using ML has the potential to similarly close the complexity gap in embedded system design, but corresponding ML-based approaches for embedded system optimization and verification at higher levels of abstraction are still at their infancy. This paper presents the current state of the art, along with opportunities and open challenges, in the application of ML methods for embedded system design and optimization. We discuss design and optimization at different levels of abstraction ranging from system-level modeling and optimization and high-level synthesis to RTL and micro-architecture design, bringing together perspectives from different communities in both academia and industry.

Hardware accelerators (HAs) underpin high-performance and energy-efficient digital systems. Correctness of these systems thus depends on the correctness of constituent HAs. Self-consistency-based pre-silicon verification techniques, like A-QED (Accelerator Quick Error Detection), provide a quick and provably thorough HA verification framework that does not require extensive design-specific properties or a full functional specification. However, A-QED is limited to verifying HAs which are non-interfering – i.e., they produce the same result for a given input independent of its context within a sequence of inputs. We present a new technique called G-QED (Generalized QED) which goes beyond non-interfering HAs while retaining A-QED’s benefits. Our extensive results as well as a detailed industrial case study show that: G-QED is highly thorough in detecting critical bugs in well-verified designs that otherwise escape traditional verification flows while simultaneously improving verification productivity 18-fold (from 370 person days to 21 person days). These results are backed by theoretical guarantees of soundness and completeness.

We present a framework that enables systematic analysis of mixed-signal application on FPGA and show its application during architecture validation of a power controller. The open source synthesizable model generator for mixed-signal blocks (msdsl) is used to create a synthesizable prototype of the analog power control application. A library of instrumentation elements enables control from a host computer, time control, analog event capture, analog stimulus and noise generation, as well as trace, read and write of arbitrary signals. This keeps the effort of building the FPGA application prototype low and provides good debugging and analysis capabilities. The end-result is a unique analysis framework for mixed-signal applications that offers almost real time analog simulation speed - thus considering software as well as analog and digital hardware - no risk of damaging equipment and simulator alike analysis and debugging capabilities at a low overhead through an instrumentation library.

The adoption of new technologies by the automotive industry drives the need for electronic component suppliers to assess and scrutinize the risk of technologies that are being integrated into the safety-critical systems. To cope with these challenges, engineers are constantly looking for highly automated and efficient functional safety approaches to achieve the required certifications for their designs. In this paper, we propose MetaFS, a metamodel-based simulator-independent fault simulation framework that provides multi-purpose fault injection strategies such as statistical fault injection, direct fault injection, and exhaustive fault injection. The framework enables the injection of stuck-at faults, single-event transients, single-event upsets as well as timing faults. The proposed approach scales to a wide range of RISC-V based CPU subsystems with support for various RISC-V ISA standard extensions and, additional safety and security related custom instruction extensions. The subsystems were running the Dhrystone application and a specific in-house Fingerprint calculation application respectively. A minimal effort of 1 person-day was required to conduct 22 different fault simulation campaigns, providing significant data regarding subsystem failure rates.

Safety-critical designs need to ensure reliable operations under hostile conditions with a certain degree of confidence. The continuously higher complexity of these designs makes them more susceptible to the risk of failure. ISO26262 recommends fault injection as the proper technique to verify and measure the dependability of safety-critical designs. To cope with the complexity, a lot of effort and stringent verification flow is needed. Moreover, many fault injection tools offer only a limited degree of controllability. We propose MetaFI, a model-driven simulator-independent fault simulation framework that provides multi-purpose fault injection strategies such as Statistical Fault Injection, Direct Fault Injection, Exhaustive Fault Injection, and at the same time reduces manual efforts. The framework enables injection of Stuck-at faults, Single-Event Transient faults, Single-Event Upset faults as well as Timing faults. The fault simulation is performed at the Register Transfer Level (RTL) of a design, in which parts of the design targeted for fault simulation are represented with Gate-level (GL) granularity. MetaFI is scalable with a full System-on-Chip (SoC) design and to demonstrate the applicability of the framework, fault simulation was applied to various components of two different SoCs. One SoC is running the Dhrystone application and the other one is running a Fingerprint calculation application. A minimal effort of 2 persondays was required to run 38 various fault injection campaigns on both the designs. The framework provided significant data regarding failure rates of the components. Results concluded that Prefetcher, a component of the SoC processor, is more susceptible to failures than the other targeted components on both the SoCs, regardless of the running application.

Nowadays, the digital chip design flow starts with formal specifications, which are mapped to Register Transfer Level (RTL) models using different underlying implementation variants and (micro-) architectures. By doing so, a hardware designer predicts and resolves time-critical parts to achieve an RTL-design that intentionally meets all constraints after synthesis. However, wrong predictions can be detected only later in the design flow, thus leading to long design iterations. Classical methods estimating delay in early design stages are constrained to the type of components or are computationally expensive for larger designs. In this paper, we propose a Machine Learning-based approach to estimate pin-to-pin delays for RTL combinational circuits. To gain accuracy, we combine slew and delay estimation. To that end, a training set is built using features of components generated by a model-driven hardware generator framework. Ground truth labels for delays, slews, and their interdependencies are extracted using open-source tools for logic synthesis and static timing analysis. Evaluations in unseen designs show that the delay estimation has on average an accuracy of 87% and it is 13x faster compared with results of synthesis and timing analysis tools. Based on the estimation, critical areas of the design can be detected and proper microarchitecture decisions can be taken earlier in the design flow.

Malware applications are one of the major threats that computing systems face today. While security researchers develop new defense mechanisms to detect malware, attackers continue to release new malware families that evade detection. New defense mechanisms must therefore be developed to effectively counter malware. Hardware performance counters (HPCs) have been recently proposed as a means to detect malware. However, recent work has also shown that malware detection is not effective when performance counters are sampled in realistic scenarios. We show how proper data preprocessing and the use of the XGBoost classifier can be used to improve the performance of malware detection using HPCs by at least 15%. We also show that the proposed method can detect malware early (shortly after its launch) by classifying HPC datastreams at short time intervals. In addition, we propose a multitemporal classification model that ensures the early detection of a high percentage of malware while maintaining overall low false positive rates. Finally, we show that through robust training, the XGBoost classifier shows up to 50x less vulnerability to adversarial attacks that are intended to undermine its malware detection performance.

The AI-hype started a few years ago, with advances in object recognition. Soon the EDA research community made proposals on applying AI in EDA and all major players announced new AI-based tools at DAC 2018. Unfortunately, few new AI-based EDA-tools made it to productive use today. This talk analyses general challenges of AI in EDA, outlines promising use cases, and motivates more AI research in EDA: More HI (=Human Intelligence) is needed to make AI successful in EDA.

Generating instead of implementing variable design platforms is becoming increasingly popular in the development of System on Chips (SoCs). This shift also poses the challenge of rapid compiler optimization that adapts to each newly generated platform. In this paper, we evaluate the impact of 104 compiler flags on memory usage and core execution time against standard optimization levels. Each flag has a different influence on these costs, which is difficult to predict. In this work, we apply cost estimation methods to predict the impact of each flag on the generated core using unsupervised Machine Learning (ML), in the form of k-means clustering. The key strengths of the approach are the low need for data, the adaptability to new cores, and the ease of use. This helps the designer to understand the impact of flags on related applications, showing which combination is optimizing the most. As a result, we can obtain 20,93% optimization on the software size, 3,10% on the performance, and 1,75% on their trade-off beyond the -03 optimization.

Developing software in a slightly different way can have a dramatic impact on soft error resilience. This observation can be transferred in a process of improving existing code by transformations. These transformations are of systematic nature and can be automated. In this paper, we present a framework for low level embedded software generation - commonly referred to as firmware - and the inclusion of safety measures in the generated code. The generation approach follows a three stage process starting with formalized firmware specification using both platform dependent and independent firmware models. Finally, C-code is generated from the view model in a straight forward way. Safety measures are included either as part of the translation step between the models or as transformations of single models.

With the advancement of Internet of Things, the cost of System-on-Chips (in terms of area, performance, etc.) becomes increasingly relevant for realizing affordable as well as performant devices. Although System-on-Chips are very diverse with respect to specifications and requirements, some components are ubiquitous. One of them is the Hardware/Software Interface, which serves for controlling communication and interconnected functionalities between Hardware and Software. Motivated by their common use, the implementation of optimized interfaces towards certain costs (in terms of area, performance, etc.) becomes a central problem in the design of embedded systems. In this work we introduce a novel optimization method for minimizing the cost of Hardware/Software Interfaces using Convolutional Neural Networks coupled with Evolutionary Algorithms.

Advancements of Machine Learning (ML) in the field of computer vision have paved the way for its potential application in many other fields. Researchers and hardware domain experts are exploring possible applications of Machine Learning in optimizing many aspects of hardware development process. In this paper, we propose a novel approach for predicting the area of hardware components from specifications. The flow uses an existing RTL generation framework, for generating valid data samples that enable ML algorithms to train the learning models. The approach has been successfully employed to predict the area of real-life hardware components such as Control and Status Register (CSR) interfaces that are ubiquitous in embedded systems. With this approach we are able to predict the area with more than 98% accuracy and 600x faster than the existing methods. In addition, we are able to rank the features according to their importance in final area estimations.

Design productivity remains a big problem in current embedded system development. Domain-Specific Languages (DSLs) are a promising measure to accelerate the development cycle. However, the inconsistent syntax in various DSLs, during system development and manual DSL development negatively impact any gained productivity. In this paper, we propose a metamodel-based framework for the generation of Python-embedded DSLs. A target metamodel abstracts models by defining elementary building blocks. With an additional configuration, our framework generates an expressive DSL which automates model construction and enables dataflow programming. By applying the proposed framework on different target meta-models, a “One Language Ecosystem” is formed with the generated DSLs describing RTL, firmware and formal properties. As a proof of concept, a System on a Chip (SoC) consisting of RTL code and a firmware stack is generated, and formal properties are automated to verify the hardware components. To develop the RTL DSL, a time reduction by a factor-of-six is observed by using this generative approach. Furthermore, by comparing the DSL description to the generated target code, a code reduction by a factor-of-eight is given.

This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.

In the last decade, several hardware generation languages (HGLs: chisel, metartl, spinalhdl, coreir and more) that focus on generation of RTL code have been proposed. These languages rise the level of abstraction from RTL description to RTL generation and utilize high-level languages such as Python or Scala for describing the generation intent. As a result, they are guiding the overall productivity and chip complexity on the rising trend. On the other front, pre-silicon verification is an equally important aspect of the design process and consumes more than 50% of the overall development time. As a consequence of increased chip complexity, the existing verification gap becomes wider. Therefore it neutralizes the productivity gain achieved from RTL generation or other productivity improvement techniques.

Although the Moore's law is slowing down in terms of technology node scaling, researchers are inventing new methods to keep the design productivity on the rising trend. As a consequence, the complexity of hardware designs will continue to grow, which results in further hardening of functional verification. Assertion based verification is well established and proven to be an effective RTL verification approach. However, manual implementation of assertions can become tedious and time consuming. Hence, a sophisticated method to automate the generation of properties from specification with minimal manual interaction is essential. In this paper, we propose a novel approach for the generation of properties that employs Object Management Group's MDA vision for code generation. The flow is built on Infineon's meta-modeling framework and makes heavy use of Python and Mako templates. Our approach incorporates model to model transformations and uses templates to finally generate the target code. Moreover, the generation flow abstracts from the property platforms and targets multiple property specification languages.

Although Moore's law is slowing down, design productivity is still a big issue in semiconductor industry. Drivers are the trend to 3D integration, the addition of design goals such as ultra-low power and safety, and an increasing number of designs in IoT and automotive areas. EDA tools such as high-level synthesis cover a small design area only. Also, the impact of IP reuse is overestimated since IP integration often requires complex configuration and additional software to be developed.To continuously increase design productivity, Infineon heavily relies on an in-house automation framework that utilizes Python as language for automation and synthesis. It supports (and makes use of) classical HDSLs to describe specific design aspects. Mostly structured specification formalisms such as tables, requirements or diagrams (e.g. SysML subsets) are used. These formalisms can be seen as HDSLs with the additional benefit that they exist as a result of a specification process, i.e. need not be coded explicitly.To be able to deal with several formalisms, Infineon's automation framework follows OMG's MDA vision and utilizes meta-models e.g. for generation of infrastructure code. This work focuses on the aspect of combining DSLs, defining a formal semantic for HDSLs and using this definition to validate the correctness of the mapping of HDSLs to HDLs, an essential pillar to connect HDSLs to today's design flows.

This paper describes the Extendable Translating Instruction Set Simulator (ETISS). In addition to binary translation, ETISS features a plugin mechanism that allows to quickly include new functionality into the translation stage, the simulation loop, during accesses to the memory or whenever an interrupt is received. ETISS targets to become an advanced industrial-strength ISS with special focus on virtual prototypes (VPs) written in SystemC/TLM. In this paper, we will show examples of ETISS Plugins, which include tracing tools, SystemC interfaces, closey-coupled peripherals or triggers for fault injection. A major drawback of developing a new binary translator such as ETISS is its lack of support for a variety of instruction set architectures (ISAs). At the moment ETISS supports the open-source OpenRISC or 1k and partly RISC-V ISAs. Yet, in order to overcome this problem, we developed a toolchain to generate the binary translation stage for different ISAs following the MDA concept based on meta-modeling and code generation. It is planned to make ETISS available as an open-source tool to the research community.

Evaluating the outcome of analog simulations is a common, mostly manually carried out task in the pre-silicon verification process of mixed-signal ICs. Its non-automated nature makes it an error-prone and time-consuming procedure. For this very reason, we introduce a novel approach for performing this evaluation automatically resulting in significantly reduced turnaround times as well as a considerably increased reliability of verification results. The presented concept is motivated by an algorithm that is used in optical pattern recognition and is called Earth Mover’s Distance. Furthermore, we compare our approach with already existing algorithms, namely Fréchet Distance and Pearson Coefficient, in order to analyze its capability. Finally, we present a case study in which we prove the algorithm by applying it to the results of a mixed-signal simulation at chip-level demonstrating the efficiency of our approach.

Evaluating the outcome of analog simulations is a common, mostly manually carried out task in the pre-silicon verification process of mixed-signal ICs. Its non-automated nature makes it an error-prone and time-consuming procedure. For this very reason, we introduce a novel approach for performing this evaluation automatically resulting in significantly reduced turnaround times as well as a considerably increased reliability of verification results. The presented concept is motivated by an algorithm that is used in optical pattern recognition and is called Earth Mover's Distance. Furthermore, we compare our approach with already existing algorithms, namely Fréchet Distance and Pearson Coefficient, in order to analyze its capability. Finally, we present a case study in which we prove the algorithm by applying it to the results of a mixed-signal simulation at chip-level demonstrating the efficiency of our approach.